memory: preliminary, regfile: more read port, decode: more correct

[firearm.git] / RegFile.v

diff --git a/RegFile.v b/RegFile.v
index 95e5c71a2fba021725dae37c488dfc73f76867e1..1e94174573cdbc82faac662c73fdc70de33e6189 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -6,6 +6,8 @@ module RegFile(
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,

+       input [3:0] read_3,
+       output reg [31:0] rdata_3,

        output reg [31:0] spsr,
        input [3:0] write,
        input write_req,
        output reg [31:0] spsr,
        input [3:0] write,
        input write_req,


@@ -49,6 +51,11 @@ module RegFile(
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];

+
+               if ((read_3 == write) && write_req)
+                       rdata_3 = write_data;
+               else
+                       rdata_3 = regfile[read_3];

                
                spsr = regfile[4'hF];
        end
                
                spsr = regfile[4'hF];
        end