DCache: Fix silly bug involving failing to clear bus_wr.

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index cd71d7628e8004cc1ca8b003a0146684e8a55278..ab204a0610a41065c5390366a38ab610b52b42e3 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -25,7 +25,8 @@ module Execute(
        output reg [31:0] jmppc,
        output reg jmp,
        output reg [31:0] outpc,
-       output reg [31:0] outinsn
+       output reg [31:0] outinsn,
+       output reg [31:0] outop0, outop1, outop2
        );
        
        reg mult_start;
@@ -69,6 +70,9 @@ module Execute(
                        write_data <= next_write_data;
                        outpc <= pc;
                        outinsn <= insn;
+                       outop0 <= op0;
+                       outop1 <= op1;
+                       outop2 <= op2;
                end
        end
 
@@ -97,7 +101,7 @@ module Execute(
                alu_setflags = 1'bx;
 
                jmp = 1'b0;
-               jmppc = 32'hxxxxxxxx;
+               jmppc = 32'h00000000;
 
                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
@@ -167,12 +171,12 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
-                       if(!inbubble) begin
+                       if(!inbubble && !flush) begin
                                jmppc = pc + op0 + 32'h8;
                                if(insn[24]) begin
                                        next_write_reg = 1;
                                        next_write_num = 4'hE; /* link register */
-                                       next_write_data = pc - 32'h4;
+                                       next_write_data = pc + 32'h4;
                                end
                                jmp = 1'b1;
                        end