input Nrst, /* XXX not used yet */
input stall, /* pipeline control */
- input flush,
+ input flush, /* XXX not used yet */
input inbubble, /* stage inputs */
input [31:0] insn,
/* XXX other? */
);
-
-
`ifdef COPY_PASTA_FODDER
/* from page 2 of ARM7TDMIvE2.pdf */
casex (insn)
- 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
-// 32'b????00001???????????????1001????: /* Multiply long */
- 32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */
- 32'b????00010?101001111100000000????: /* MSR (Transfer register to PSR) */
- 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
- 32'b????00??????????????????????????: /* ALU */
- 32'b????00010?00????????00001001????: /* Atomic swap */
- 32'b????000100101111111111110001????: /* Branch */
- 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
- 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */
- 32'b????011????????????????????1????: /* Undefined. I hate ARM */
- 32'b????01??????????????????????????: /* Single data transfer */
- 32'b????100?????????????????????????: /* Block data transfer */
- 32'b????101?????????????????????????: /* Branch */
- 32'b????110?????????????????????????: /* Coprocessor data transfer */
- 32'b????1110???????????????????0????: /* Coprocessor data op */
- 32'b????1110???????????????????1????: /* Coprocessor register transfer */
- 32'b????1111????????????????????????: /* SWI */
- default: /* X everything else out */
+ `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+// `DECODE_ALU_MUL_LONG: /* Multiply long */
+ `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
+ `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
+ `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ `DECODE_ALU_SWP: /* Atomic swap */
+ `DECODE_ALU_BX: /* Branch */
+ `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
+ `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
+ `DECODE_ALU: /* ALU */
+ `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
+ `DECODE_LDRSTR: /* Single data transfer */
+ `DECODE_LDMSTM: /* Block data transfer */
+ `DECODE_BRANCH: /* Branch */
+ `DECODE_LDCSTC: /* Coprocessor data transfer */
+ `DECODE_CDP: /* Coprocessor data op */
+ `DECODE_MRCMCR: /* Coprocessor register transfer */
+ `DECODE_SWI: /* SWI */
+ default: /* X everything else out */
endcase
`endif
always @(*)
casez (insn)
- 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+ `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
def_cpsr = insn[20] /* setcc */;
def_regs = idxbit(rd_mul);
end
-// 32'b????00001???????????????1001????: /* Multiply long */
- 32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */
+// `DECODE_ALU_MUL_LONG: /* Multiply long */
+ `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
begin
use_cpsr = `COND_MATTERS(cond) || (insn[22] == 0) /* Source = CPSR */;
use_regs = 0;
def_cpsr = 0;
def_regs = idxbit(rd);
end
- 32'b????00010?101001111100000000????: /* MSR (Transfer register to PSR) */
+ `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = idxbit(rm);
def_cpsr = 1;
def_regs = 0;
end
- 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = insn[25] ? 0 : idxbit(rm);
def_cpsr = 1;
def_regs = 0;
end
- 32'b????00??????????????????????????: /* ALU */
+ `DECODE_ALU: /* ALU */
begin
use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
use_regs =
def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc);
def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
end
- 32'b????00010?00????????00001001????: /* Atomic swap */
+ `DECODE_ALU_SWP: /* Atomic swap */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = idxbit(rn) | idxbit(rm);
def_cpsr = 0;
def_regs = idxbit(rd);
end
- 32'b????000100101111111111110001????: /* Branch */
+ `DECODE_ALU_BX: /* Branch */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = idxbit(rm);
def_cpsr = 0; // don't care, we'll never get there
def_regs = 0;
end
- 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
+ `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = idxbit(rn) | idxbit(rm) | (insn[20] /* L */ ? 0 : idxbit(rd));
def_cpsr = 0;
def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
end
- 32'b????000??1??????????00001??1????: /* Halfword transfer - immediate offset */
+ `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
def_cpsr = 0;
def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
end
- 32'b????011????????????????????1????: /* Undefined. I hate ARM */
+ `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
begin
use_cpsr = 0;
use_regs = 0;
def_cpsr = 0;
def_regs = 0;
end
- 32'b????100?????????????????????????: /* Block data transfer */
+ `DECODE_LDRSTR:
+ begin
+ use_cpsr = `COND_MATTERS(cond);
+ use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
+ def_cpsr = 0;
+ def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+ end
+ `DECODE_LDMSTM: /* Block data transfer */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : insn[15:0]);
def_cpsr = insn[22]; /* This is a superset of all cases, anyway. */
def_regs = (insn[21] /* W */ ? idxbit(rn) : 0) | (insn[20] /* L */ ? insn[15:0] : 0);
end
- 32'b????101?????????????????????????: /* Branch */
+ `DECODE_BRANCH: /* Branch */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = 0;
def_cpsr = 0;
def_regs = 0;
end
- 32'b????110?????????????????????????: /* Coprocessor data transfer */
+ `DECODE_LDCSTC: /* Coprocessor data transfer */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = idxbit(rn);
def_cpsr = 0;
def_regs = insn[21] /* W */ ? idxbit(rn) : 0;
end
- 32'b????1110???????????????????0????: /* Coprocessor data op */
+ `DECODE_CDP: /* Coprocessor data op */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = 0;
def_cpsr = 0;
def_regs = 0;
end
- 32'b????1110???????????????????1????: /* Coprocessor register transfer */
+ `DECODE_MRCMCR: /* Coprocessor register transfer */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = insn[20] /* L */ ? 0 : idxbit(rd);
def_cpsr = 0;
def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
end
- 32'b????1111????????????????????????: /* SWI */
+ `DECODE_SWI: /* SWI */
begin
use_cpsr = `COND_MATTERS(cond);
use_regs = 0;
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