Add a jump test

[firearm.git] / system.v

diff --git a/system.v b/system.v
index 685d5bd20d7070c65a5c0edaf25a1dc70d9a9747..8ab3e23cb6370b8cac6853d58d21610b90410b91 100644 (file)
--- a/system.v
+++ b/system.v
@@ -27,7 +27,7 @@ module System(input clk);
        assign bus_rd = bus_rd_icache;
        assign bus_wr = bus_wr_icache;
        assign bus_ready = bus_ready_blockram;
        assign bus_rd = bus_rd_icache;
        assign bus_wr = bus_wr_icache;
        assign bus_ready = bus_ready_blockram;

-       
+

        wire [31:0] icache_rd_addr;
        wire icache_rd_req;
        wire icache_rd_wait;
        wire [31:0] icache_rd_addr;
        wire icache_rd_req;
        wire icache_rd_wait;


@@ -36,14 +36,16 @@ module System(input clk);
        wire stall_cause_issue;
        wire stall_cause_execute;
        
        wire stall_cause_issue;
        wire stall_cause_execute;
        

-       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2;
+       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;

        wire decode_out_carry;
        wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
        wire decode_out_carry;
        wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;

-       wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2;
+       wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;

        wire execute_out_stall, execute_out_bubble;
        wire execute_out_write_reg;
        wire [3:0] execute_out_write_num;
        wire [31:0] execute_out_write_data;
        wire execute_out_stall, execute_out_bubble;
        wire execute_out_write_reg;
        wire [3:0] execute_out_write_num;
        wire [31:0] execute_out_write_data;

+       wire [31:0] jmppc;
+       wire jmp;

        
        wire bubble_out_fetch;
        wire bubble_out_issue;
        
        wire bubble_out_fetch;
        wire bubble_out_issue;


@@ -51,7 +53,7 @@ module System(input clk);
        wire [31:0] insn_out_issue;
        wire [31:0] pc_out_fetch;
        wire [31:0] pc_out_issue;
        wire [31:0] insn_out_issue;
        wire [31:0] pc_out_fetch;
        wire [31:0] pc_out_issue;

-       
+

        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
        ICache icache(
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
        ICache icache(


@@ -75,7 +77,7 @@ module System(input clk);
                .Nrst(1'b1 /* XXX */),
                .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
                .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
                .Nrst(1'b1 /* XXX */),
                .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
                .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),

-               .stall(stall_cause_issue), .jmp(1'b0 /* XXX */), .jmppc(32'b0 /* XXX */),
+               .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),

                .bubble(bubble_out_fetch), .insn(insn_out_fetch),
                .pc(pc_out_fetch));
        
                .bubble(bubble_out_fetch), .insn(insn_out_fetch),
                .pc(pc_out_fetch));
        


@@ -92,13 +94,13 @@ module System(input clk);
                .clk(clk),
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
                .clk(clk),
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),

-               .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
+               .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));

        
        Decode decode(
                .clk(clk),
        
        Decode decode(
                .clk(clk),

-               .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */),
+               .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),

                .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
                .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),

-               .carry(decode_out_carry),
+               .carry(decode_out_carry), .outspsr(decode_out_spsr),

                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
        
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
        


@@ -106,12 +108,14 @@ module System(input clk);
                .clk(clk), .Nrst(1'b0),
                .stall(1'b0 /* XXX */), .flush(1'b0 /* XXX */),
                .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
                .clk(clk), .Nrst(1'b0),
                .stall(1'b0 /* XXX */), .flush(1'b0 /* XXX */),
                .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),

-               .cpsr(32'b0 /* XXX */), .op0(decode_out_op0), .op1(decode_out_op1),
+               .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),

                .op2(decode_out_op2), .carry(decode_out_carry),
                .outstall(stall_cause_execute), .outbubble(execute_out_bubble),
                .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
                .op2(decode_out_op2), .carry(decode_out_carry),
                .outstall(stall_cause_execute), .outbubble(execute_out_bubble),
                .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),

-               .write_data(execute_out_write_data));
-       
+               .write_data(execute_out_write_data),
+               .jmppc(jmppc),
+               .jmp(jmp));
+

        reg [31:0] clockno = 0;
        always @(posedge clk)
        begin
        reg [31:0] clockno = 0;
        always @(posedge clk)
        begin


@@ -120,6 +124,6 @@ module System(input clk);
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
                $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
                $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);

-               $display("%3d: EXEC:   Stall: %d, Bubble: %d, Output: %d, [%08x -> %d]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num);
+               $display("%3d: EXEC:   Stall: %d, Bubble: %d, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);

        end
 endmodule
        end
 endmodule