tests/Makefile: Add a target to pad binaries for Xilinx tools.

[firearm.git] / Issue.v

diff --git a/Issue.v b/Issue.v
index 1b9868da1a2b7b0236b58dc2382960961805c89f..153f25f65c85176700001e8f671e8b683bc63dd4 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -12,7 +12,7 @@ module Issue(
        input [31:0] inpc,
        input [31:0] cpsr,
        
-       output reg outstall = 0,        /* stage outputs */
+       output wire outstall,   /* stage outputs */
        output reg outbubble = 1,
        output reg [31:0] outpc = 0,
        output reg [31:0] outinsn = 0
@@ -196,7 +196,7 @@ module Issue(
                        use_cpsr = `COND_MATTERS(cond);
                        use_regs = 0;
                        def_cpsr = 0;
-                       def_regs = 0;
+                       def_regs = insn[24] /* L */ ? (16'b1 << 14) : 0;
                end
                `DECODE_LDCSTC: /* Coprocessor data transfer */
                begin
@@ -265,10 +265,6 @@ module Issue(
        reg cpsr_inflight [1:0];
        reg [15:0] regs_inflight [1:0];
        
-       reg waiting_cpsr;
-       reg waiting_regs;
-       wire waiting = waiting_cpsr | waiting_regs;
-       
        initial
        begin
                cpsr_inflight[0] = 0;
@@ -276,14 +272,11 @@ module Issue(
                regs_inflight[0] = 0;
                regs_inflight[1] = 0;
        end
-               
-       always @(*)
-       begin
-               waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
-               waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
-               
-               outstall = (waiting && !inbubble && !flush) || stall;   /* Happens in an always @*, because it is an exception. */
-       end
+       
+       wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
+       wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
+       wire waiting = waiting_cpsr | waiting_regs;
+       assign outstall = (waiting && !inbubble && !flush) || stall;
 
        reg delayedflush = 0;
        always @(posedge clk)
@@ -291,29 +284,21 @@ module Issue(
                        delayedflush <= 1;
                else if (!outstall /* anything has been handled this time around */)
                        delayedflush <= 0;
-       
+
        /* Actually do the issue. */
        always @(posedge clk)
        begin
                if (waiting)
                        $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
 
-               if((flush || delayedflush) && !outstall)
-               begin
-                       cpsr_inflight[0] = 1'b0;
-                       cpsr_inflight[1] = 1'b0;
-                       regs_inflight[0] = 16'b0;
-                       regs_inflight[1] = 16'b0;
-                       outbubble <= 1'b1;
-               end
-               else if (!stall)
+               if (!stall)
                begin
                        cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
                        cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
                        regs_inflight[0] <= regs_inflight[1];
                        regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
                        
-                       outbubble <= inbubble | waiting | !condition_met;
+                       outbubble <= inbubble | waiting | !condition_met | flush | delayedflush;
                        outpc <= inpc;
                        outinsn <= insn;
                end