Issue: Fix use_regs for LDRSTR when not acting on an immediate value.

[firearm.git] / Issue.v

diff --git a/Issue.v b/Issue.v
index ef53bc3ed932365292c5969a7a95b7f74d88f42f..1b9868da1a2b7b0236b58dc2382960961805c89f 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -180,7 +180,7 @@ module Issue(
                `DECODE_LDRSTR:
                begin
                        use_cpsr = `COND_MATTERS(cond);
-                       use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
+                       use_regs = idxbit(rn) | (insn[25] /* I */ ? idxbit(rm) : 0) | (insn[20] /* L */ ? 0 : idxbit(rd));
                        def_cpsr = 0;
                        def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
                end
@@ -282,8 +282,15 @@ module Issue(
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
                
-               outstall = (waiting && !inbubble) || stall;     /* Happens in an always @*, because it is an exception. */
+               outstall = (waiting && !inbubble && !flush) || stall;   /* Happens in an always @*, because it is an exception. */
        end
+
+       reg delayedflush = 0;
+       always @(posedge clk)
+               if (flush && outstall /* halp! I can't do it now, maybe later? */)
+                       delayedflush <= 1;
+               else if (!outstall /* anything has been handled this time around */)
+                       delayedflush <= 0;
        
        /* Actually do the issue. */
        always @(posedge clk)
@@ -291,12 +298,13 @@ module Issue(
                if (waiting)
                        $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
 
-               if(flush)
+               if((flush || delayedflush) && !outstall)
                begin
                        cpsr_inflight[0] = 1'b0;
                        cpsr_inflight[1] = 1'b0;
                        regs_inflight[0] = 16'b0;
                        regs_inflight[1] = 16'b0;
+                       outbubble <= 1'b1;
                end
                else if (!stall)
                begin
@@ -305,7 +313,7 @@ module Issue(
                        regs_inflight[0] <= regs_inflight[1];
                        regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
                        
-                       outbubble <= inbubble | waiting | !condition_met | flush;
+                       outbubble <= inbubble | waiting | !condition_met;
                        outpc <= inpc;
                        outinsn <= insn;
                end