DCache: Fix silly bug involving failing to clear bus_wr.

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index cefc4ef00d2c0d23535f938e3c3e91494764e25b..ab204a0610a41065c5390366a38ab610b52b42e3 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -23,7 +23,10 @@ module Execute(
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,
        output reg [31:0] jmppc,
-       output reg jmp
+       output reg jmp,
+       output reg [31:0] outpc,
+       output reg [31:0] outinsn,
+       output reg [31:0] outop0, outop1, outop2
        );
        
        reg mult_start;
@@ -65,6 +68,11 @@ module Execute(
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
+                       outpc <= pc;
+                       outinsn <= insn;
+                       outop0 <= op0;
+                       outop1 <= op1;
+                       outop2 <= op2;
                end
        end
 
@@ -93,7 +101,7 @@ module Execute(
                alu_setflags = 1'bx;
 
                jmp = 1'b0;
-               jmppc = 32'hxxxxxxxx;
+               jmppc = 32'h00000000;
 
                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
@@ -163,13 +171,15 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
-                       jmppc = pc + op0 + 32'h8;
-                       if(insn[24]) begin
-                               next_write_reg = 1;
-                               next_write_num = 4'hE; /* link register */
-                               next_write_data = pc + 32'h4;
+                       if(!inbubble && !flush) begin
+                               jmppc = pc + op0 + 32'h8;
+                               if(insn[24]) begin
+                                       next_write_reg = 1;
+                                       next_write_num = 4'hE; /* link register */
+                                       next_write_data = pc + 32'h4;
+                               end
+                               jmp = 1'b1;
                        end
-                       jmp = 1'b1;
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */
                `DECODE_CDP,            /* Coprocessor data op */
@@ -234,8 +244,8 @@ module ALU(
        output reg [31:0] cpsr_out,
        output reg setres
 );
-       wire [31:0] res;
-       wire flag_n, flag_z, flag_c, flag_v, setres;
+       reg [31:0] res;
+       reg flag_n, flag_z, flag_c, flag_v;
        wire [32:0] sum, diff, rdiff;
        wire sum_v, diff_v, rdiff_v;