Decode: Fix stupid bug in which stalls did not stall the decoder.
[firearm.git] / Decode.v
index 90ac3d6..c63fd9d 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -2,6 +2,7 @@
 
 module Decode(
        input clk,
+       input stall,
        input [31:0] insn,
        input [31:0] inpc,
        input [31:0] incpsr,
@@ -10,6 +11,7 @@ module Decode(
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg carry,
+       output reg [31:0] outcpsr,
        output reg [31:0] outspsr,
 
        output reg [3:0] read_0,
@@ -138,16 +140,20 @@ module Decode(
                begin
                        read_0 = insn[19:16];
                        read_1 = insn[3:0];
-                       
+                       read_2 = insn[15:12];
+
                        op0_out = regs0;
                        op1_out = regs1;
+                       op2_out = regs2;
                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        read_0 = insn[19:16];
+                       read_1 = insn[15:12];
                        
                        op0_out = regs0;
                        op1_out = {24'b0, insn[11:8], insn[3:0]};
+                       op2_out = regs1;
                end
                `DECODE_ALU:            /* ALU */
                begin
@@ -221,11 +227,15 @@ module Decode(
 
        
        always @ (posedge clk) begin
-               op0 <= op0_out;   /* Rn - always */
-               op1 <= op1_out; /* 'operand 2' - Rm */
-               op2 <= op2_out;   /* thirdedge - Rs */
-               carry <= carry_out;
-               outspsr <= inspsr;
+               if (!stall)
+               begin
+                       op0 <= op0_out;   /* Rn - always */
+                       op1 <= op1_out; /* 'operand 2' - Rm */
+                       op2 <= op2_out;   /* thirdedge - Rs */
+                       carry <= carry_out;
+                       outcpsr <= incpsr;
+                       outspsr <= inspsr;
+               end
        end
 
 endmodule
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