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1 | module RegFile( | |
2 | input clk, | |
3 | input Nrst, | |
4 | input [3:0] read_0, | |
5 | output wire [31:0] rdata_0, | |
6 | input [3:0] read_1, | |
7 | output wire [31:0] rdata_1, | |
8 | input [3:0] read_2, | |
9 | output wire [31:0] rdata_2, | |
10 | input [3:0] read_3, | |
11 | output wire [31:0] rdata_3, | |
12 | output wire [31:0] spsr, | |
13 | input write, | |
14 | input [3:0] write_reg, | |
15 | input [31:0] write_data | |
16 | ); | |
17 | ||
18 | reg [31:0] regfile [0:15]; | |
19 | integer i; | |
20 | ||
21 | initial begin | |
22 | for (i = 0; i < 16; i = i + 1) | |
23 | regfile[i] = 0; | |
24 | end | |
25 | ||
26 | assign rdata_0 = ((read_0 == write_reg) && write) ? write_data : regfile[read_0]; | |
27 | assign rdata_1 = ((read_1 == write_reg) && write) ? write_data : regfile[read_1]; | |
28 | assign rdata_2 = ((read_2 == write_reg) && write) ? write_data : regfile[read_2]; | |
29 | assign rdata_3 = ((read_3 == write_reg) && write) ? write_data : regfile[read_3]; | |
30 | assign spsr = regfile[4'hF]; | |
31 | ||
32 | always @(posedge clk or negedge Nrst) | |
33 | if (!Nrst) begin | |
34 | for (i = 0; i < 16; i = i + 1) | |
35 | regfile[i] <= 0; | |
36 | end else if (write) | |
37 | regfile[write_reg] <= write_data; | |
38 | endmodule |