Joshua Wise's Git repositories - firearm.git/blame_incremental

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Commit	Line	Data
	1	`define COND_EQ 4'b0000 /* Z set */
	2	`define COND_NE 4'b0001 /* Z clear */
	3	`define COND_CS 4'b0010 /* C set */
	4	`define COND_CC 4'b0011 /* C clear */
	5	`define COND_MI 4'b0100 /* N set */
	6	`define COND_PL 4'b0101 /* N clear */
	7	`define COND_VS 4'b0110 /* V set */
	8	`define COND_VC 4'b0111 /* V clear */
	9	`define COND_HI 4'b1000 /* C set and Z clear */
	10	`define COND_LS 4'b1001 /* C clear or Z set */
	11	`define COND_GE 4'b1010 /* N equal to V */
	12	`define COND_LT 4'b1011 /* N not equal to V */
	13	`define COND_GT 4'b1100 /* Z clear AND (N equals V) */
	14	`define COND_LE 4'b1101 /* Z set OR (N not equals V) */
	15	`define COND_AL 4'b1110 /* TRUE */
	16	`define COND_NV 4'b1111 /* FALSE */
	17
	18	`define COND_MATTERS(x) ((x != `COND_AL) && (x != `COND_NV))
	19
	20	`define ALU_AND 4'b0000
	21	`define ALU_EOR 4'b0001
	22	`define ALU_SUB 4'b0010
	23	`define ALU_RSB 4'b0011
	24	`define ALU_ADD 4'b0100
	25	`define ALU_ADC 4'b0101
	26	`define ALU_SBC 4'b0110
	27	`define ALU_RSC 4'b0111
	28	`define ALU_TST 4'b1000
	29	`define ALU_TEQ 4'b1001
	30	`define ALU_CMP 4'b1010
	31	`define ALU_CMN 4'b1011
	32	`define ALU_ORR 4'b1100
	33	`define ALU_MOV 4'b1101
	34	`define ALU_BIC 4'b1110
	35	`define ALU_MVN 4'b1111
	36
	37	`define SHIFT_LSL 2'b00
	38	`define SHIFT_LSR 2'b01
	39	`define SHIFT_ASR 2'b10
	40	`define SHIFT_ROR 2'b11
	41
	42	`define CPSR_N 31
	43	`define CPSR_Z 30
	44	`define CPSR_C 29
	45	`define CPSR_V 28
	46	`define CPSR_I 7
	47	`define CPSR_F 6
	48
	49	`define SHIFT_LSL 2'b00
	50	`define SHIFT_LSR 2'b01
	51	`define SHIFT_ASR 2'b10
	52	`define SHIFT_ROR 2'b11
	53
	54	`define DECODE_ALU_MULT 32'b????000000??????????????1001???? /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	55	`define DECODE_ALU_MUL_LONG 32'b????00001???????????????1001???? /* Multiply long */
	56	`define DECODE_ALU_MRS 32'b????00010?001111????000000000000 /* MRS (Transfer PSR to register) */
	57	`define DECODE_ALU_MSR 32'b????00010?101001111100000000???? /* MSR (Transfer register to PSR) */
	58	`define DECODE_ALU_MSR_FLAGS 32'b????00?10?1010001111???????????? /* MSR (Transfer register or immediate to PSR, flag bits only) */
	59	`define DECODE_ALU_SWP 32'b????00010?00????????00001001???? /* Atomic swap */
	60	`define DECODE_ALU_BX 32'b????000100101111111111110001???? /* Branch and exchange */
	61	`define DECODE_ALU_HDATA_REG 32'b????000??0??????????00001??1???? /* Halfword transfer - register offset */
	62	`define DECODE_ALU_HDATA_IMM 32'b????000??1??????????00001??1???? /* Halfword transfer - immediate offset */
	63	`define DECODE_ALU 32'b????00?????????????????????????? /* ALU */
	64	`define DECODE_LDRSTR_UNDEFINED 32'b????011????????????????????1???? /* Undefined. I hate ARM */
	65	`define DECODE_LDRSTR 32'b????01?????????????????????????? /* Single data transfer */
	66	`define DECODE_LDMSTM 32'b????100????????????????????????? /* Block data transfer */
	67	`define DECODE_BRANCH 32'b????101????????????????????????? /* Branch */
	68	`define DECODE_LDCSTC 32'b????110????????????????????????? /* Coprocessor data transfer */
	69	`define DECODE_CDP 32'b????1110???????????????????0???? /* Coprocessor data op */
	70	`define DECODE_MRCMCR 32'b????1110???????????????????1???? /* Coprocessor register transfer */
	71	`define DECODE_SWI 32'b????1111???????????????????????? /* SWI */
	72
	73	`define MODE_USR 5'b10000
	74	`define MODE_FIQ 5'b10001
	75	`define MODE_IRQ 5'b10010
	76	`define MODE_SVC 5'b10011
	77	`define MODE_ABT 5'b10111
	78	`define MODE_UND 5'b11011
	79	`define MODE_SYS 5'b11111