st_data -> op2
[firearm.git] / system.v
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1`define BUS_ICACHE 0
2`define BUS_DCACHE 1
3
4module System(input clk);
5 wire [7:0] bus_req;
6 wire [7:0] bus_ack;
7 wire [31:0] bus_addr;
8 wire [31:0] bus_rdata;
9 wire [31:0] bus_wdata;
10 wire bus_rd, bus_wr;
11 wire bus_ready;
12
13 wire bus_req_icache;
14 wire bus_req_dcache;
15 assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
16 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
17 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
18
19 wire [31:0] bus_addr_icache;
20 wire [31:0] bus_wdata_icache;
21 wire bus_rd_icache;
22 wire bus_wr_icache;
23
24 wire [31:0] bus_addr_dcache;
25 wire [31:0] bus_wdata_dcache;
26 wire bus_rd_dcache;
27 wire bus_wr_dcache;
28
29 wire [31:0] bus_rdata_blockram;
30 wire bus_ready_blockram;
31
32 assign bus_addr = bus_addr_icache | bus_addr_dcache;
33 assign bus_rdata = bus_rdata_blockram;
34 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
35 assign bus_rd = bus_rd_icache | bus_rd_dcache;
36 assign bus_wr = bus_wr_icache | bus_wr_dcache;
37 assign bus_ready = bus_ready_blockram;
38
39 wire [31:0] icache_rd_addr;
40 wire icache_rd_req;
41 wire icache_rd_wait;
42 wire [31:0] icache_rd_data;
43
44 wire [31:0] dcache_addr;
45 wire dcache_rd_req, dcache_wr_req;
46 wire dcache_rw_wait;
47 wire [31:0] dcache_wr_data, dcache_rd_data;
48
49 wire stall_cause_issue;
50 wire stall_cause_execute;
51
52 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
53 wire decode_out_carry;
54 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
55 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
56 wire execute_out_write_reg;
57 wire [3:0] execute_out_write_num;
58 wire [31:0] execute_out_write_data;
59 wire [31:0] jmppc;
60 wire jmp;
61
62 wire bubble_out_fetch;
63 wire bubble_out_issue;
64 wire bubble_out_execute;
65 wire [31:0] insn_out_fetch;
66 wire [31:0] insn_out_issue;
67 wire [31:0] insn_out_execute;
68 wire [31:0] pc_out_fetch;
69 wire [31:0] pc_out_issue;
70 wire [31:0] pc_out_execute;
71
72 wire execute_out_backflush;
73
74 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
75
76 ICache icache(
77 .clk(clk),
78 /* XXX reset? */
79 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
80 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
81 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
82 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
83 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
84 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
85
86 DCache dcache(
87 .clk(clk),
88 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
89 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
90 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
91 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
92 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
93 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
94
95 BlockRAM blockram(
96 .clk(clk),
97 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
98 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
99 .bus_ready(bus_ready_blockram));
100
101 Fetch fetch(
102 .clk(clk),
103 .Nrst(1'b1 /* XXX */),
104 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
105 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
106 .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
107 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
108 .pc(pc_out_fetch));
109
110 Issue issue(
111 .clk(clk),
112 .Nrst(1'b1 /* XXX */),
113 .stall(stall_cause_execute), .flush(execute_out_backflush),
114 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
115 .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
116 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
117 .outpc(pc_out_issue), .outinsn(insn_out_issue));
118
119 RegFile regfile(
120 .clk(clk),
121 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
122 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
123 .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
124
125 Decode decode(
126 .clk(clk),
127 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
128 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
129 .carry(decode_out_carry), .outspsr(decode_out_spsr),
130 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
131 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
132
133 Execute execute(
134 .clk(clk), .Nrst(1'b0),
135 .stall(1'b0 /* XXX */), .flush(1'b0),
136 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
137 .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
138 .op2(decode_out_op2), .carry(decode_out_carry),
139 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
140 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
141 .write_data(execute_out_write_data),
142 .jmp(jmp), .jmppc(jmppc),
143 .outpc(pc_out_execute), .outinsn(insn_out_execute));
144 assign execute_out_backflush = jmp;
145
146 reg [31:0] clockno = 0;
147 always @(posedge clk)
148 begin
149 clockno <= clockno + 1;
150 $display("------------------------------------------------------------------------------");
151 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
152 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
153 $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
154 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
155 end
156endmodule
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