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1 | /* 16 cache entries, 64-byte long cache lines */ | |
2 | ||
3 | module DCache( | |
4 | input clk, | |
5 | ||
6 | /* ARM core interface */ | |
7 | input [31:0] addr, | |
8 | input rd_req, | |
9 | input wr_req, | |
10 | output reg rw_wait, | |
11 | input [31:0] wr_data, | |
12 | output reg [31:0] rd_data, | |
13 | ||
14 | /* bus interface */ | |
15 | output wire bus_req, | |
16 | input bus_ack, | |
17 | output reg [31:0] bus_addr = 0, | |
18 | input [31:0] bus_rdata, | |
19 | output reg [31:0] bus_wdata, | |
20 | output reg bus_rd = 0, | |
21 | output reg bus_wr = 0, | |
22 | input bus_ready); | |
23 | ||
24 | /* [31 tag 10] [9 cache index 6] [5 data index 0] | |
25 | * so the data index is 6 bits long | |
26 | * so the cache index is 4 bits long | |
27 | * so the tag is 22 bits long. c.c | |
28 | */ | |
29 | ||
30 | reg cache_valid [15:0]; | |
31 | reg [21:0] cache_tags [15:0]; | |
32 | reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */]; | |
33 | ||
34 | reg [4:0] i; | |
35 | initial | |
36 | for (i = 0; i < 16; i = i + 1) | |
37 | begin | |
38 | cache_valid[i[3:0]] = 0; | |
39 | cache_tags[i[3:0]] = 0; | |
40 | end | |
41 | ||
42 | wire [5:0] didx = addr[5:0]; | |
43 | wire [3:0] didx_word = didx[5:2]; | |
44 | wire [3:0] idx = addr[9:6]; | |
45 | wire [21:0] tag = addr[31:10]; | |
46 | ||
47 | wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag); | |
48 | ||
49 | always @(*) begin | |
50 | rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready)); | |
51 | rd_data = cache_data[idx][didx_word]; | |
52 | end | |
53 | ||
54 | reg [3:0] cache_fill_pos = 0; | |
55 | assign bus_req = (rd_req && !cache_hit) || wr_req; | |
56 | always @(*) | |
57 | if (rd_req && !cache_hit && bus_ack) begin | |
58 | bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */}; | |
59 | bus_rd = 1; | |
60 | end else if (wr_req && bus_ack) begin | |
61 | bus_addr = addr; | |
62 | bus_wr = 1; | |
63 | bus_wdata = wr_data; | |
64 | end else begin | |
65 | bus_addr = 0; | |
66 | bus_rd = 0; | |
67 | end | |
68 | ||
69 | always @(posedge clk) | |
70 | if (rd_req && !cache_hit) begin | |
71 | if (bus_ready) begin /* Started the fill, and we have data. */ | |
72 | cache_data[idx][cache_fill_pos] <= bus_rdata; | |
73 | cache_fill_pos <= cache_fill_pos + 1; | |
74 | if (cache_fill_pos == 15) begin /* Done? */ | |
75 | cache_tags[idx] <= tag; | |
76 | cache_valid[idx] <= 1; | |
77 | end | |
78 | end | |
79 | end else if (wr_req && cache_hit) | |
80 | cache_data[idx][addr[5:2]] = wr_data; | |
81 | endmodule |