| 1 | `define BUS_ICACHE 0 |
| 2 | |
| 3 | module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc); |
| 4 | wire [7:0] bus_req; |
| 5 | wire [7:0] bus_ack; |
| 6 | wire [31:0] bus_addr; |
| 7 | wire [31:0] bus_rdata; |
| 8 | wire [31:0] bus_wdata; |
| 9 | wire bus_rd, bus_wr; |
| 10 | wire bus_ready; |
| 11 | |
| 12 | wire bus_req_icache = bus_req[`BUS_ICACHE]; |
| 13 | wire bus_ack_icache = bus_ack[`BUS_ICACHE]; |
| 14 | wire [31:0] bus_addr_icache; |
| 15 | wire [31:0] bus_wdata_icache; |
| 16 | wire bus_rd_icache; |
| 17 | wire bus_wr_icache; |
| 18 | |
| 19 | wire [31:0] bus_rdata_blockram; |
| 20 | wire bus_ready_blockram; |
| 21 | |
| 22 | assign bus_addr = bus_addr_icache; |
| 23 | assign bus_rdata = bus_rdata_blockram; |
| 24 | assign bus_wdata = bus_wdata_icache; |
| 25 | assign bus_rd = bus_rd_icache; |
| 26 | assign bus_wr = bus_wr_icache; |
| 27 | assign bus_ready = bus_ready_blockram; |
| 28 | |
| 29 | wire [31:0] icache_rd_addr; |
| 30 | wire icache_rd_req; |
| 31 | wire icache_rd_wait; |
| 32 | wire [31:0] icache_rd_data; |
| 33 | |
| 34 | BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack)); |
| 35 | |
| 36 | ICache icache( |
| 37 | .clk(clk), |
| 38 | /* XXX reset? */ |
| 39 | .rd_addr(icache_rd_addr), .rd_req(icache_rd_req), |
| 40 | .rd_wait(icache_rd_wait), .rd_data(icache_rd_data), |
| 41 | .bus_req(bus_req_icache), .bus_ack(bus_ack_icache), |
| 42 | .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata), |
| 43 | .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache), |
| 44 | .bus_wr(bus_wr_icache), .bus_ready(bus_ready)); |
| 45 | |
| 46 | BlockRAM blockram( |
| 47 | .clk(clk), |
| 48 | .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram), |
| 49 | .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr), |
| 50 | .bus_ready(bus_ready_blockram)); |
| 51 | |
| 52 | Fetch fetch( |
| 53 | .clk(clk), |
| 54 | .Nrst(1 /* XXX */), |
| 55 | .rd_addr(icache_rd_addr), .rd_req(icache_rd_req), |
| 56 | .rd_wait(icache_rd_wait), .rd_data(icache_rd_data), |
| 57 | .stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */), |
| 58 | .bubble(bubbleshield), .insn(insn), .pc(pc)); |
| 59 | |
| 60 | endmodule |