Memory: Add CDP and MRC/MCR.
[firearm.git] / system.v
... / ...
CommitLineData
1`define BUS_ICACHE 0
2`define BUS_DCACHE 1
3
4module System(input clk);
5 wire [7:0] bus_req;
6 wire [7:0] bus_ack;
7 wire [31:0] bus_addr;
8 wire [31:0] bus_rdata;
9 wire [31:0] bus_wdata;
10 wire bus_rd, bus_wr;
11 wire bus_ready;
12
13 wire bus_req_icache;
14 wire bus_req_dcache;
15 assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
16 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
17 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
18
19 wire [31:0] bus_addr_icache;
20 wire [31:0] bus_wdata_icache;
21 wire bus_rd_icache;
22 wire bus_wr_icache;
23
24 wire [31:0] bus_addr_dcache;
25 wire [31:0] bus_wdata_dcache;
26 wire bus_rd_dcache;
27 wire bus_wr_dcache;
28
29 wire [31:0] bus_rdata_blockram;
30 wire bus_ready_blockram;
31
32 assign bus_addr = bus_addr_icache | bus_addr_dcache;
33 assign bus_rdata = bus_rdata_blockram;
34 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
35 assign bus_rd = bus_rd_icache | bus_rd_dcache;
36 assign bus_wr = bus_wr_icache | bus_wr_dcache;
37 assign bus_ready = bus_ready_blockram;
38
39 wire [31:0] icache_rd_addr;
40 wire icache_rd_req;
41 wire icache_rd_wait;
42 wire [31:0] icache_rd_data;
43
44 wire [31:0] dcache_addr;
45 wire dcache_rd_req, dcache_wr_req;
46 wire dcache_rw_wait;
47 wire [31:0] dcache_wr_data, dcache_rd_data;
48
49 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
50 wire decode_out_carry;
51
52 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
53 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
54
55 wire execute_out_write_reg;
56 wire [3:0] execute_out_write_num;
57 wire [31:0] execute_out_write_data;
58 wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
59 wire [31:0] jmppc;
60 wire jmp;
61
62 wire memory_out_write_reg;
63 wire [3:0] memory_out_write_num;
64 wire [31:0] memory_out_write_data;
65
66 wire cp_req;
67 wire cp_ack = 0;
68 wire cp_busy = 0;
69 wire cp_rnw;
70 wire [31:0] cp_read = 0;
71 wire [31:0] cp_write;
72
73 wire stall_cause_issue;
74 wire stall_cause_execute;
75 wire stall_cause_memory;
76 wire bubble_out_fetch;
77 wire bubble_out_issue;
78 wire bubble_out_execute;
79 wire bubble_out_memory;
80 wire [31:0] insn_out_fetch;
81 wire [31:0] insn_out_issue;
82 wire [31:0] insn_out_execute;
83 wire [31:0] insn_out_memory;
84 wire [31:0] pc_out_fetch;
85 wire [31:0] pc_out_issue;
86 wire [31:0] pc_out_execute;
87 wire [31:0] pc_out_memory;
88
89 wire execute_out_backflush;
90
91 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
92
93 ICache icache(
94 .clk(clk),
95 /* XXX reset? */
96 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
97 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
98 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
99 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
100 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
101 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
102
103 DCache dcache(
104 .clk(clk),
105 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
106 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
107 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
108 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
109 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
110 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
111
112 BlockRAM blockram(
113 .clk(clk),
114 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
115 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
116 .bus_ready(bus_ready_blockram));
117
118 Fetch fetch(
119 .clk(clk),
120 .Nrst(1'b1 /* XXX */),
121 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
122 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
123 .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
124 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
125 .pc(pc_out_fetch));
126
127 Issue issue(
128 .clk(clk),
129 .Nrst(1'b1 /* XXX */),
130 .stall(stall_cause_execute), .flush(execute_out_backflush),
131 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
132 .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
133 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
134 .outpc(pc_out_issue), .outinsn(insn_out_issue));
135
136 RegFile regfile(
137 .clk(clk),
138 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_2(regfile_read_3),
139 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_2(regfile_rdata_3),
140 .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
141
142 Decode decode(
143 .clk(clk),
144 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
145 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
146 .carry(decode_out_carry), .outspsr(decode_out_spsr),
147 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
148 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
149
150 Execute execute(
151 .clk(clk), .Nrst(1'b0),
152 .stall(stall_cause_memory), .flush(1'b0),
153 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
154 .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
155 .op2(decode_out_op2), .carry(decode_out_carry),
156 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
157 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
158 .write_data(execute_out_write_data),
159 .jmp(jmp), .jmppc(jmppc),
160 .outpc(pc_out_execute), .outinsn(insn_out_execute),
161 .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2));
162 assign execute_out_backflush = jmp;
163
164 Memory memory(
165 .clk(clk), .Nrst(1'b0),
166 /* stall? flush? */
167 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
168 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
169 .st_read(regfile_read_3), .st_data(regfile_rdata_3),
170 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
171 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
172 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
173 .outstall(stall_cause_memory), .outbubble(bubble_out_memory),
174 .outpc(pc_out_memory), .outinsn(insn_out_memory),
175 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
176 .out_write_data(memory_out_write_data),
177 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write));
178
179 reg [31:0] clockno = 0;
180 always @(posedge clk)
181 begin
182 clockno <= clockno + 1;
183 $display("------------------------------------------------------------------------------");
184 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
185 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
186 $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
187 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
188 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
189 end
190endmodule
This page took 0.016871 seconds and 4 git commands to generate.