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ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency. ...
[firearm.git] / xst / impact.cmd
... / ...
CommitLineData
1setMode -bs
2setCable -port svf -file "XXX.svf"
3addDevice -p 1 -file "XXX.bit"
4addDevice -p 2 -part xcf04s
5Program -p 1 -defaultVersion 0
6quit
7
FireARM pipelined ARM-like CPU implementation in Verilog
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