system: Wire up outcpsr and outspsr from Execute to Memory.
[firearm.git] / system.v
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1`define BUS_ICACHE 0
2`define BUS_DCACHE 1
3
4module System(input clk);
5 wire [7:0] bus_req;
6 wire [7:0] bus_ack;
7 wire [31:0] bus_addr;
8 wire [31:0] bus_rdata;
9 wire [31:0] bus_wdata;
10 wire bus_rd, bus_wr;
11 wire bus_ready;
12
13 wire bus_req_icache;
14 wire bus_req_dcache;
15 assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
16 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
17 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
18
19 wire [31:0] bus_addr_icache;
20 wire [31:0] bus_wdata_icache;
21 wire bus_rd_icache;
22 wire bus_wr_icache;
23
24 wire [31:0] bus_addr_dcache;
25 wire [31:0] bus_wdata_dcache;
26 wire bus_rd_dcache;
27 wire bus_wr_dcache;
28
29 wire [31:0] bus_rdata_blockram;
30 wire bus_ready_blockram;
31
32 assign bus_addr = bus_addr_icache | bus_addr_dcache;
33 assign bus_rdata = bus_rdata_blockram;
34 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
35 assign bus_rd = bus_rd_icache | bus_rd_dcache;
36 assign bus_wr = bus_wr_icache | bus_wr_dcache;
37 assign bus_ready = bus_ready_blockram;
38
39 wire [31:0] icache_rd_addr;
40 wire icache_rd_req;
41 wire icache_rd_wait;
42 wire [31:0] icache_rd_data;
43
44 wire [31:0] dcache_addr;
45 wire dcache_rd_req, dcache_wr_req;
46 wire dcache_rw_wait;
47 wire [31:0] dcache_wr_data, dcache_rd_data;
48
49 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
50 wire decode_out_carry;
51
52 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
53 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
54
55 wire execute_out_write_reg;
56 wire [3:0] execute_out_write_num;
57 wire [31:0] execute_out_write_data;
58 wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
59 wire [31:0] execute_out_cpsr, execute_out_spsr;
60 wire [31:0] jmppc;
61 wire jmp;
62
63 wire memory_out_write_reg;
64 wire [3:0] memory_out_write_num;
65 wire [31:0] memory_out_write_data;
66
67 wire cp_req;
68 wire cp_ack = 0;
69 wire cp_busy = 0;
70 wire cp_rnw;
71 wire [31:0] cp_read = 0;
72 wire [31:0] cp_write;
73
74 wire stall_cause_issue;
75 wire stall_cause_execute;
76 wire stall_cause_memory;
77 wire bubble_out_fetch;
78 wire bubble_out_issue;
79 wire bubble_out_execute;
80 wire bubble_out_memory;
81 wire [31:0] insn_out_fetch;
82 wire [31:0] insn_out_issue;
83 wire [31:0] insn_out_execute;
84 wire [31:0] insn_out_memory;
85 wire [31:0] pc_out_fetch;
86 wire [31:0] pc_out_issue;
87 wire [31:0] pc_out_execute;
88 wire [31:0] pc_out_memory;
89
90 wire execute_out_backflush;
91
92 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
93
94 ICache icache(
95 .clk(clk),
96 /* XXX reset? */
97 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
98 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
99 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
100 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
101 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
102 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
103
104 DCache dcache(
105 .clk(clk),
106 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
107 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
108 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
109 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
110 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
111 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
112
113 BlockRAM blockram(
114 .clk(clk),
115 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
116 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
117 .bus_ready(bus_ready_blockram));
118
119 Fetch fetch(
120 .clk(clk),
121 .Nrst(1'b1 /* XXX */),
122 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
123 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
124 .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
125 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
126 .pc(pc_out_fetch));
127
128 Issue issue(
129 .clk(clk),
130 .Nrst(1'b1 /* XXX */),
131 .stall(stall_cause_execute), .flush(execute_out_backflush),
132 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
133 .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
134 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
135 .outpc(pc_out_issue), .outinsn(insn_out_issue));
136
137 RegFile regfile(
138 .clk(clk),
139 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_2(regfile_read_3),
140 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_2(regfile_rdata_3),
141 .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
142
143 Decode decode(
144 .clk(clk),
145 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
146 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
147 .carry(decode_out_carry), .outspsr(decode_out_spsr),
148 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
149 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
150
151 Execute execute(
152 .clk(clk), .Nrst(1'b0),
153 .stall(stall_cause_memory), .flush(1'b0),
154 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
155 .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
156 .op2(decode_out_op2), .carry(decode_out_carry),
157 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
158 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
159 .write_data(execute_out_write_data),
160 .jmp(jmp), .jmppc(jmppc),
161 .outpc(pc_out_execute), .outinsn(insn_out_execute),
162 .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
163 .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr));
164 assign execute_out_backflush = jmp;
165
166 Memory memory(
167 .clk(clk), .Nrst(1'b0),
168 /* stall? flush? */
169 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
170 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
171 .st_read(regfile_read_3), .st_data(regfile_rdata_3),
172 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
173 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
174 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr),
175 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
176 .outstall(stall_cause_memory), .outbubble(bubble_out_memory),
177 .outpc(pc_out_memory), .outinsn(insn_out_memory),
178 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
179 .out_write_data(memory_out_write_data),
180 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write));
181
182 reg [31:0] clockno = 0;
183 always @(posedge clk)
184 begin
185 clockno <= clockno + 1;
186 $display("------------------------------------------------------------------------------");
187 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
188 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
189 $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
190 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
191 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
192 end
193endmodule
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