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Commit | Line | Data |
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1 | module Execute( | |
2 | input clk, | |
3 | input Nrst, /* XXX not used yet */ | |
4 | ||
5 | input stall, | |
6 | input flush, | |
7 | ||
8 | input inbubble, | |
9 | input [31:0] pc, | |
10 | input [31:0] insn, | |
11 | input [31:0] cpsr, | |
12 | input [31:0] op0, | |
13 | input [31:0] op1, | |
14 | input [31:0] op2, | |
15 | input carry, | |
16 | ||
17 | output reg outstall = 0, | |
18 | output reg outbubble = 1 | |
19 | ); | |
20 | ||
21 | endmodule | |
22 | ||
23 | module Multiplier( | |
24 | input clk, | |
25 | input Nrst, /* XXX not used yet */ | |
26 | ||
27 | input start, | |
28 | input [31:0] acc0, | |
29 | input [31:0] in0, | |
30 | input [31:0] in1, | |
31 | ||
32 | output reg done = 0, | |
33 | output reg [31:0] result); | |
34 | ||
35 | reg [31:0] bitfield; | |
36 | reg [31:0] multiplicand; | |
37 | reg [31:0] acc; | |
38 | ||
39 | always @(posedge clk) | |
40 | begin | |
41 | if (start) begin | |
42 | bitfield <= in0; | |
43 | multiplicand <= in1; | |
44 | acc <= acc0; | |
45 | done <= 0; | |
46 | end else begin | |
47 | bitfield <= {2'b00, bitfield[31:2]}; | |
48 | multiplicand <= {multiplicand[29:0], 2'b00}; | |
49 | acc <= acc + | |
50 | (bitfield[0] ? multiplicand : 0) + | |
51 | (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0); | |
52 | if (bitfield == 0) begin | |
53 | result <= acc; | |
54 | done <= 1; | |
55 | end | |
56 | end | |
57 | end | |
58 | endmodule |