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[firearm.git] / Memory.v
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1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
6
7 input flush,
8
9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
16 output reg [2:0] data_size,
17
18 /* regfile interface */
19 output reg [3:0] st_read,
20 input [31:0] st_data,
21
22 /* Coprocessor interface */
23 output reg cp_req,
24 input cp_ack,
25 input cp_busy,
26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
27 input [31:0] cp_read,
28 output reg [31:0] cp_write,
29
30 /* stage inputs */
31 input inbubble,
32 input [31:0] pc,
33 input [31:0] insn,
34 input [31:0] op0,
35 input [31:0] op1,
36 input [31:0] op2,
37 input [31:0] spsr,
38 input [31:0] cpsr,
39 input cpsrup,
40 input write_reg,
41 input [3:0] write_num,
42 input [31:0] write_data,
43
44 /* outputs */
45 output reg outstall,
46 output reg outbubble,
47 output reg [31:0] outpc,
48 output reg [31:0] outinsn,
49 output reg out_write_reg = 1'b0,
50 output reg [3:0] out_write_num = 4'bxxxx,
51 output reg [31:0] out_write_data = 32'hxxxxxxxx,
52 output reg [31:0] outspsr = 32'hxxxxxxxx,
53 output reg [31:0] outcpsr = 32'hxxxxxxxx,
54 output reg outcpsrup = 1'hx
55 );
56
57 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
58 reg next_outcpsrup;
59 reg [31:0] prevaddr;
60 reg [3:0] next_regsel, cur_reg, prev_reg;
61 reg next_writeback;
62
63 reg next_outbubble;
64 reg next_write_reg;
65 reg [3:0] next_write_num;
66 reg [31:0] next_write_data;
67
68 reg [2:0] lsr_state = 3'b001, next_lsr_state;
69 reg [31:0] align_s1, align_s2, align_rddata;
70
71 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
72 reg [31:0] lsrh_rddata;
73 reg [15:0] lsrh_rddata_s1;
74 reg [7:0] lsrh_rddata_s2;
75
76 reg [15:0] regs, next_regs;
77 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
78 reg [5:0] offset, prev_offset, offset_sel;
79
80 reg [31:0] swp_oldval, next_swp_oldval;
81 reg [1:0] swp_state = 2'b01, next_swp_state;
82
83 always @(posedge clk)
84 begin
85 outpc <= pc;
86 outinsn <= insn;
87 outbubble <= next_outbubble;
88 out_write_reg <= next_write_reg;
89 out_write_num <= next_write_num;
90 out_write_data <= next_write_data;
91 regs <= next_regs;
92 prev_reg <= cur_reg;
93 if (!rw_wait)
94 prev_offset <= offset;
95 prev_raddr <= raddr;
96 outcpsr <= next_outcpsr;
97 outspsr <= spsr;
98 outcpsrup <= next_outcpsrup;
99 swp_state <= next_swp_state;
100 lsm_state <= next_lsm_state;
101 lsr_state <= next_lsr_state;
102 lsrh_state <= next_lsrh_state;
103 prevaddr <= addr;
104 end
105
106 reg delayedflush = 0;
107 always @(posedge clk)
108 if (flush && outstall /* halp! I can't do it now, maybe later? */)
109 delayedflush <= 1;
110 else if (!outstall /* anything has been handled this time around */)
111 delayedflush <= 0;
112
113 always @(*)
114 begin
115 addr = prevaddr;
116 raddr = 32'hxxxxxxxx;
117 rd_req = 1'b0;
118 wr_req = 1'b0;
119 wr_data = 32'hxxxxxxxx;
120 busaddr = 32'hxxxxxxxx;
121 data_size = 3'bxxx;
122 outstall = 1'b0;
123 next_write_reg = write_reg;
124 next_write_num = write_num;
125 next_write_data = write_data;
126 next_outbubble = inbubble;
127 next_regs = regs;
128 cp_req = 1'b0;
129 cp_rnw = 1'bx;
130 cp_write = 32'hxxxxxxxx;
131 offset = prev_offset;
132 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
133 next_outcpsrup = cpsrup;
134 lsrh_rddata = 32'hxxxxxxxx;
135 lsrh_rddata_s1 = 16'hxxxx;
136 lsrh_rddata_s2 = 8'hxx;
137 next_lsm_state = lsm_state;
138 next_lsr_state = lsr_state;
139 next_lsrh_state = lsrh_state;
140 next_swp_oldval = swp_oldval;
141 next_swp_state = swp_state;
142 cur_reg = prev_reg;
143
144 /* XXX shit not given about endianness */
145 casez(insn)
146 `DECODE_ALU_SWP: if(!inbubble) begin
147 outstall = rw_wait;
148 next_outbubble = rw_wait;
149 busaddr = {op0[31:2], 2'b0};
150 data_size = insn[22] ? 3'b001 : 3'b100;
151 case(swp_state)
152 2'b01: begin
153 rd_req = 1'b1;
154 outstall = 1'b1;
155 if(!rw_wait) begin
156 next_swp_state = 2'b10;
157 next_swp_oldval = rd_data;
158 end
159 $display("SWP: read stage");
160 end
161 2'b10: begin
162 wr_req = 1'b1;
163 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
164 next_write_reg = 1'b1;
165 next_write_num = insn[15:12];
166 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
167 if(!rw_wait)
168 next_swp_state = 2'b01;
169 $display("SWP: write stage");
170 end
171 default: begin end
172 endcase
173 end
174 `DECODE_ALU_MULT: begin end
175 `DECODE_ALU_HDATA_REG,
176 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
177 next_outbubble = rw_wait;
178 outstall = rw_wait;
179 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
180 raddr = insn[24] ? op0 : addr; /* pre/post increment */
181 busaddr = raddr;
182 /* rotate to correct position */
183 case(insn[6:5])
184 2'b00: begin end /* swp */
185 2'b01: begin /* unsigned half */
186 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
187 data_size = 3'b010;
188 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
189 end
190 2'b10: begin /* signed byte */
191 wr_data = {4{op2[7:0]}};
192 data_size = 3'b001;
193 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
194 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
195 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
196 end
197 2'b11: begin /* signed half */
198 wr_data = {2{op2[15:0]}};
199 data_size = 3'b010;
200 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
201 end
202 endcase
203
204 case(lsrh_state)
205 3'b001: begin
206 rd_req = insn[20];
207 wr_req = ~insn[20];
208 next_write_num = insn[15:12];
209 next_write_data = lsrh_rddata;
210 if(insn[20]) begin
211 next_write_reg = 1'b1;
212 end
213 if(insn[21] | !insn[24]) begin
214 outstall = 1'b1;
215 if(!rw_wait)
216 next_lsrh_state = 3'b010;
217 end
218 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
219 end
220 3'b010: begin
221 next_outbubble = 1'b0;
222 next_write_reg = 1'b1;
223 next_write_num = insn[19:16];
224 next_write_data = addr;
225 next_lsrh_state = 3'b100;
226 end
227 3'b100: begin
228 outstall = 0;
229 next_lsrh_state = 3'b001;
230 end
231 default: begin end
232 endcase
233
234 if ((lsrh_state == 3'b001) && flush) begin /* Reject it. */
235 outstall = 1'b0;
236 next_lsrh_state = 3'b001;
237 end
238 end
239 `DECODE_LDRSTR_UNDEFINED: begin end
240 `DECODE_LDRSTR: if(!inbubble) begin
241 next_outbubble = rw_wait;
242 outstall = rw_wait;
243 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
244 raddr = insn[24] ? addr : op0; /* pre/post increment */
245 busaddr = raddr;
246 /* rotate to correct position */
247 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
248 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
249 /* select byte or word */
250 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
251 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
252 data_size = insn[22] ? 3'b001 : 3'b100;
253 case(lsr_state)
254 3'b001: begin
255 rd_req = insn[20] /* L */;
256 wr_req = ~insn[20] /* L */;
257 next_write_reg = insn[20] /* L */;
258 next_write_num = insn[15:12];
259 if(insn[20] /* L */) begin
260 next_write_data = align_rddata;
261 end
262 if(insn[21] /* W */ | !insn[24] /* P */) begin
263 outstall = 1'b1;
264 if(!rw_wait)
265 next_lsr_state = 3'b010;
266 end
267 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
268 end
269 3'b010: begin
270 outstall = 1;
271 next_outbubble = 0;
272 next_write_reg = 1'b1;
273 next_write_num = insn[19:16];
274 next_write_data = addr;
275 next_lsr_state = 3'b100;
276 end
277 3'b100: begin
278 outstall = 0;
279 next_lsr_state = 3'b001;
280 end
281 default: begin end
282 endcase
283
284 if ((lsr_state == 3'b001) && flush) begin /* Reject it. */
285 outstall = 1'b0;
286 next_lsr_state = 3'b001;
287 end
288 end
289 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
290 `DECODE_LDMSTM: if(!inbubble) begin
291 outstall = rw_wait;
292 next_outbubble = rw_wait;
293 data_size = 3'b100;
294 case(lsm_state)
295 4'b0001: begin
296// next_regs = insn[23] ? op1[15:0] : op1[0:15];
297 /** verilator can suck my dick */
298 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
299 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
300 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
301 offset = 6'b0;
302 outstall = 1'b1;
303 next_lsm_state = 4'b0010;
304 end
305 4'b0010: begin
306 rd_req = insn[20];
307 wr_req = ~insn[20];
308 casez(regs)
309 16'b???????????????1: begin
310 cur_reg = 4'h0;
311 next_regs = {regs[15:1], 1'b0};
312 end
313 16'b??????????????10: begin
314 cur_reg = 4'h1;
315 next_regs = {regs[15:2], 2'b0};
316 end
317 16'b?????????????100: begin
318 cur_reg = 4'h2;
319 next_regs = {regs[15:3], 3'b0};
320 end
321 16'b????????????1000: begin
322 cur_reg = 4'h3;
323 next_regs = {regs[15:4], 4'b0};
324 end
325 16'b???????????10000: begin
326 cur_reg = 4'h4;
327 next_regs = {regs[15:5], 5'b0};
328 end
329 16'b??????????100000: begin
330 cur_reg = 4'h5;
331 next_regs = {regs[15:6], 6'b0};
332 end
333 16'b?????????1000000: begin
334 cur_reg = 4'h6;
335 next_regs = {regs[15:7], 7'b0};
336 end
337 16'b????????10000000: begin
338 cur_reg = 4'h7;
339 next_regs = {regs[15:8], 8'b0};
340 end
341 16'b???????100000000: begin
342 cur_reg = 4'h8;
343 next_regs = {regs[15:9], 9'b0};
344 end
345 16'b??????1000000000: begin
346 cur_reg = 4'h9;
347 next_regs = {regs[15:10], 10'b0};
348 end
349 16'b?????10000000000: begin
350 cur_reg = 4'hA;
351 next_regs = {regs[15:11], 11'b0};
352 end
353 16'b????100000000000: begin
354 cur_reg = 4'hB;
355 next_regs = {regs[15:12], 12'b0};
356 end
357 16'b???1000000000000: begin
358 cur_reg = 4'hC;
359 next_regs = {regs[15:13], 13'b0};
360 end
361 16'b??10000000000000: begin
362 cur_reg = 4'hD;
363 next_regs = {regs[15:14], 14'b0};
364 end
365 16'b?100000000000000: begin
366 cur_reg = 4'hE;
367 next_regs = {regs[15], 15'b0};
368 end
369 16'b1000000000000000: begin
370 cur_reg = 4'hF;
371 next_regs = 16'b0;
372 end
373 default: begin
374 cur_reg = 4'hx;
375 next_regs = 16'b0;
376 end
377 endcase
378 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
379 if(cur_reg == 4'hF && insn[22]) begin
380 next_outcpsr = spsr;
381 next_outcpsrup = 1;
382 end
383
384 offset = prev_offset + 6'h4;
385 offset_sel = insn[24] ? offset : prev_offset;
386 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
387 if(insn[20]) begin
388 next_write_reg = !rw_wait;
389 next_write_num = cur_reg;
390 next_write_data = rd_data;
391 end
392 if (rw_wait) begin
393 next_regs = regs;
394 cur_reg = prev_reg; /* whoops, do this one again */
395 end
396
397 st_read = cur_reg;
398 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
399 busaddr = raddr;
400
401 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
402
403 outstall = 1'b1;
404
405 if(next_regs == 16'b0) begin
406 next_lsm_state = 4'b0100;
407 end
408 end
409 4'b0100: begin
410 outstall = 1;
411 next_outbubble = 0;
412 next_write_reg = insn[21] /* writeback */;
413 next_write_num = insn[19:16];
414 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
415 next_lsm_state = 4'b1000;
416 $display("LDMSTM: Stage 3: Writing back");
417 end
418 4'b1000: begin
419 outstall = 0;
420 next_lsm_state = 4'b0001;
421 end
422 default: $stop;
423 endcase
424 if ((lsm_state == 4'b0001) && flush) begin /* Reject it. */
425 outstall = 1'b0;
426 next_lsm_state = 4'b0001;
427 end
428 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
429 end
430 `DECODE_LDCSTC: if(!inbubble) begin
431 $display("WARNING: Unimplemented LDCSTC");
432 end
433 `DECODE_CDP: if(!inbubble) begin
434 cp_req = 1;
435 if (cp_busy) begin
436 outstall = 1;
437 next_outbubble = 1;
438 end
439 if (!cp_ack) begin
440 /* XXX undefined instruction trap */
441 $display("WARNING: Possible CDP undefined instruction");
442 end
443 end
444 `DECODE_MRCMCR: if(!inbubble) begin
445 cp_req = 1;
446 cp_rnw = insn[20] /* L */;
447 if (insn[20] == 0 /* store to coprocessor */)
448 cp_write = op0;
449 else begin
450 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
451 next_write_reg = 1'b1;
452 next_write_num = insn[15:12];
453 next_write_data = cp_read;
454 end else begin
455 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
456 next_outcpsrup = 1;
457 end
458 end
459 if (cp_busy) begin
460 outstall = 1;
461 next_outbubble = 1;
462 end
463 if (!cp_ack) begin
464 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
465 end
466 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
467 end
468 default: begin end
469 endcase
470
471 if ((flush || delayedflush) && !outstall)
472 next_outbubble = 1'b1;
473 end
474endmodule
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