ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency. ...
[firearm.git] / Makefile
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1VLOGS = ARM_Constants.v BigBlockRAM.v BlockRAM.v BusArbiter.v DCache.v Decode.v Execute.v Fetch.v ICache.v Issue.v Memory.v Minishift.v RegFile.v Terminal.v Writeback.v system.v
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3all: Vsystem
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5Vsystem: obj_dir/Vsystem.mk testbench.cpp
6 make -C obj_dir -f Vsystem.mk
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8obj_dir/Vsystem.mk: $(VLOGS)
9 mkdir -p obj_dir
10 verilator --cc system.v testbench.cpp --exe
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12auto: .DUMMY
13 emacs -l ~/elisp/verilog-mode.el --batch system.v -f verilog-batch-auto
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6d8250a2 15.DUMMY:
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