From: Joshua Wise <jwise@andrew.cmu.edu>
Date: Mon, 5 Jul 2010 09:57:19 +0000 (-0400)
Subject: woo it generated some code
X-Git-Url: http://git.joshuawise.com/snipe.git/commitdiff_plain/de034162d9af50e6bfb454f4de67213d856137c4?ds=sidebyside;hp=4a34fbf0834d02dd913bf872e45b3285aafce641

woo it generated some code
---

diff --git a/codegen/blarg.sml b/codegen/blarg.sml
index ab48de1..aacc993 100644
--- a/codegen/blarg.sml
+++ b/codegen/blarg.sml
@@ -134,6 +134,7 @@ struct
     | regtonum R1 = 1
     | regtonum R2 = 2
     | regtonum R3 = 3
+    | regtonum SP = 4
     | regtonum _ = raise ErrorMsg.InternalError ("regtonum: Invalid register")
 
   (* gives reg associated with number (color) *)
diff --git a/codegen/codegen.sml b/codegen/codegen.sml
index aad1770..8181905 100644
--- a/codegen/codegen.sml
+++ b/codegen/codegen.sml
@@ -125,9 +125,9 @@ struct
     (*| munch_exp d (T.BINOP(T.SUB, e1, T.CONST n)) = binophit_c d X.SUB e1 n
     | munch_exp d (T.BINOP(T.SUB, e1, T.TEMP t)) = binophit_t d X.SUB e1 t*)
     | munch_exp d (T.BINOP(T.SUB, e1, e2)) = binophit d X.SUB e1 e2
-    | munch_exp d (T.BINOP(T.MUL, _, _)) = raise ErrorMsg.InternalError "MUL does not exist on blargcpu"
-    | munch_exp d (T.BINOP(T.DIV, _, _)) = raise ErrorMsg.InternalError "DIV does not exist on blargcpu"
-    | munch_exp d (T.BINOP(T.MOD, _, _)) = raise ErrorMsg.InternalError "MOD does not exist on blargcpu"
+    | munch_exp d (T.BINOP(T.MUL, e1, e2)) = munch_exp d (T.CALL (Symbol.symbol "__blarg_mul", [e1, e2]))
+    | munch_exp d (T.BINOP(T.DIV, e1, e2)) = munch_exp d (T.CALL (Symbol.symbol "__blarg_div", [e1, e2]))
+    | munch_exp d (T.BINOP(T.MOD, e1, e2)) = munch_exp d (T.CALL (Symbol.symbol "__blarg_mod", [e1, e2]))
     | munch_exp d (T.BINOP(T.LSH, e1, e2)) = binophit d X.SHL e1 e2
     | munch_exp d (T.BINOP(T.RSH, e1, e2)) = binophit d X.SHR e1 e2
     | munch_exp d (T.BINOP(T.BITAND, e1, e2)) = binophit d X.AND e1 e2
diff --git a/sources.cm b/sources.cm
index edf6e49..e10115a 100644
--- a/sources.cm
+++ b/sources.cm
@@ -35,7 +35,7 @@ Group is
 	codegen/liveness.sml
 	codegen/igraph.sml
 	codegen/colororder.sml
-	codegen/solidify.sml
+(*	codegen/solidify.sml*)
 	codegen/coloring.sml
 	codegen/stringifier.sml
 
diff --git a/top/top.sml b/top/top.sml
index 5263317..6a132c6 100644
--- a/top/top.sml
+++ b/top/top.sml
@@ -34,7 +34,7 @@ struct
      FeckfulnessAnalysis.optimizer,
      ConstantFold.optimizer,
      LabelCoalescing.optimizer,
-     Peephole.optimizer*)]
+     Peephole.optimizer*)] : Optimizer.optimization list
   
   val uniqopts =
     foldr
@@ -107,7 +107,7 @@ struct
         val _ = Flag.guard Flags.verbose say "  Generating proto-x86_64 code..."
         val assem = Codegen.codegen ir
         val _ = Flag.guard Flags.assem
-                  (fn () => List.app (TextIO.print o (x86.print)) assem) ()
+                  (fn () => List.app (TextIO.print o (Blarg.print)) assem) ()
 
         val _ = Flag.guard Flags.verbose say "  Optimizing pre-liveness..."
         val assem = Optimizer.optimize_preliveness (!enabledopts) assem
@@ -119,7 +119,7 @@ struct
                     (fn (asm, liv) =>
                       TextIO.print (
                         let
-                          val xpp = x86.print asm
+                          val xpp = Blarg.print asm
                           val xpp = String.extract (xpp, 0, SOME (size xpp - 1))
                           val spaces = implode (List.tabulate (40 - size xpp, fn _ => #" ")) handle size => ""
                           val lpp = Liveness.prettyprint liv
@@ -142,14 +142,14 @@ struct
                   (fn () => List.app (TextIO.print o
                     (fn (t, i) =>
                       (Temp.name t) ^ " => " ^ (
-                        if (i <= x86.regtonum x86.R13D)
-                          then (x86.pp_oper (x86.REG (x86.numtoreg i), Temp.Long))
+                        if (i <= Blarg.regtonum Blarg.R3)
+                          then (Blarg.pp_oper (Blarg.REG (Blarg.numtoreg i)))
                         else
-                          "spill[" ^ Int.toString (i - x86.regtonum x86.R13D) ^ "]")
+                          "spill[" ^ Int.toString (i - Blarg.regtonum Blarg.R3) ^ "]")
                         ^ "--"^ Int.toString i ^ "\n"))
                     colors) ()
 
-        val _ = Flag.guard Flags.verbose say "  Solidifying x86_64 code..."
+(*        val _ = Flag.guard Flags.verbose say "  Solidifying blargCPU code..."
         val x86 = Solidify.solidify colors assem
 
         val _ = Flag.guard Flags.verbose say "  Optimizing final assembly..."
@@ -159,9 +159,9 @@ struct
         val x86d = [x86.DIRECTIVE(".globl " ^ name),
                     x86.DIRECTIVE(name ^ ":")]
                     @ x86p
-        val code = Stringify.stringify realname x86d
+        val code = Stringify.stringify realname x86d*)
       in
-        code
+        ""
       end
 
   fun main (name, args) =