From 0170e492f95ac26a3f0efb18bbfa60e619935b63 Mon Sep 17 00:00:00 2001
From: Jacob Potter <jdpotter@andrew.cmu.edu>
Date: Sat, 23 Apr 2011 04:38:32 -0400
Subject: [PATCH] It lives!

---
 POSLink.ucf |  2 +-
 POSLink.v   | 26 +++++++++++++-------------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/POSLink.ucf b/POSLink.ucf
index 7409bdd..6ac74b3 100644
--- a/POSLink.ucf
+++ b/POSLink.ucf
@@ -1,4 +1,4 @@
-NET "xtal" LOC="P1";
+NET "xtal" LOC="P43";
 NET "xtal" BUFG=CLK;
 
 NET "tos_inputs_e2<0>" LOC="P38";
diff --git a/POSLink.v b/POSLink.v
index b53c08f..323e0d4 100644
--- a/POSLink.v
+++ b/POSLink.v
@@ -38,6 +38,7 @@ module POSLink(
 
 	reg [1:0] tos_select;
 
+wire [4:0] edge_counter;
 	wire [3:0] current_bit;
 
 	assign tos_output = tos_inputs_e2[tos_select];
@@ -47,14 +48,14 @@ module POSLink(
 		seg = data[9:8];
 		tos_select = data[11:10];
 	end
-	
+
 	wire [5:0] output_stuff = { buttons, tos_good };
 
 	always @(*)
 		data_output = output_stuff[current_bit[2:0]];
 
 	TOS_Detect detect[3:0](.xtal(xtal), .tos_input(tos_inputs), .tos_good(tos_good));
-	POS_Serial serinput(.xtal(xtal), .serial(serial), .data_reg(data), .current_bit(current_bit), .data_good(data_good));
+	POS_Serial serinput(.xtal(xtal), .serial(serial), .data_reg(data), .current_bit(current_bit), .data_good(data_good), .edge_counter(edge_counter));
 endmodule
 
 
@@ -63,39 +64,38 @@ module POS_Serial(
 	input serial,
 	output reg [11:0] data_reg = 0,
 	output reg [3:0] current_bit = 0,
+	output reg [4:0] edge_counter = 0,
 	output reg data_good = 0);
 
 	reg serial_1a;
 
 	always @(posedge xtal)
-		serial_1a = serial;
+		serial_1a <= serial;
 
 	wire edge_detect = serial ^ serial_1a;
 
-	reg [4:0] edge_counter = 0;
 
 	always @(posedge xtal) begin
-		data_good = 0;
+		data_good <= 0;
 
 		if (edge_detect) begin
 			if (edge_counter == 31) begin
-				current_bit = 0;
-				data_reg = 0;
+				current_bit <= 0;
+//				data_reg <= 0;
 			end else begin
 		//		data_reg[11:1] = data_reg[10:0];
 		//		data_reg[0] = (edge_counter > 20);
-				data_reg[current_bit] = (edge_counter > 20);
+				data_reg[current_bit] <= ((edge_counter > 20) ? 1'b1 : 1'b0);
 				if (current_bit == 11) begin
-					data_good = 1;
-					current_bit = 0;
+					current_bit <= 0;
 				end else
-					current_bit = current_bit + 1;
+					current_bit <= current_bit + 1;
 			end
 
-			edge_counter = 0;
+			edge_counter <= 0;
 		end else begin
 			if (edge_counter != 31)
-				edge_counter = edge_counter + 1;
+				edge_counter <= edge_counter + 1;
 		end
 	end
 endmodule
-- 
2.39.2