From d38897859a6ae318f7356987d8d8fcd6446e962f Mon Sep 17 00:00:00 2001
From: Jacob Potter <jdpotter@andrew.cmu.edu>
Date: Sat, 23 Apr 2011 13:12:09 -0400
Subject: [PATCH] whoops.

---
 Makefile    |  2 +-
 POSLink.ucf | 10 +++++-----
 POSLink.v   |  9 +++++----
 3 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/Makefile b/Makefile
index aab7d17..f6ef7b2 100644
--- a/Makefile
+++ b/Makefile
@@ -42,7 +42,7 @@ $(TARGET).ngd: $(TARGET).ngc $(TARGET).ucf
 	ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p $(CHIP) "$(TARGET).ngc" $(TARGET).ngd
 
 $(TARGET).vm6: $(TARGET).ngd
-	cpldfit -p $(CHIP) -power std $(TARGET).ngd -inputs 10 
+	cpldfit -p $(CHIP) -power std $(TARGET).ngd -inputs 12 -pterms 10 
 
 $(TARGET).jed: $(TARGET).vm6
 	hprep6 -i $(TARGET).vm6
diff --git a/POSLink.ucf b/POSLink.ucf
index b9f3ece..2a9cbd7 100644
--- a/POSLink.ucf
+++ b/POSLink.ucf
@@ -1,11 +1,11 @@
 NET "xtal" LOC="P43";
 NET "xtal" BUFG=CLK;
 
-NET "tos_inputs_e2<0>" LOC="P38";
-NET "tos_inputs_e2<1>" LOC="P39";
-NET "tos_inputs_e2<2>" LOC="P32";
-NET "tos_inputs_e2<3>" LOC="P31";
-NET "tos_output"       LOC="P30";
+NET "tos_inputs_e2<0>" LOC="P30";
+NET "tos_inputs_e2<1>" LOC="P31";
+NET "tos_inputs_e2<2>" LOC="P38";
+NET "tos_inputs_e2<3>" LOC="P39";
+NET "tos_output"       LOC="P32";
 NET "data_output"      LOC="P3";
 NET "serial_e2"        LOC="P2";
 NET "anode<0>"         LOC="P29";
diff --git a/POSLink.v b/POSLink.v
index ce96bd0..6428436 100644
--- a/POSLink.v
+++ b/POSLink.v
@@ -5,8 +5,8 @@ module POSLink(
 	input [1:0] buttons,
 	output tos_output,
 	output reg data_output,
-	output reg [3:0] anode,
-	output reg [7:0] cathode);
+	output reg [3:0] anode = 4'hF,
+	output reg [7:0] cathode = 8'hFF);
 	
 	reg [3:0] tos_inputs_e;
 	reg [3:0] tos_inputs;
@@ -49,7 +49,8 @@ wire [4:0] edge_counter;
 		tos_select = data[11:10];
 	end
 
-	wire [7:0] output_stuff = { 2'b0, buttons, tos_good };
+	// Buttons are active-low, so invert them. 
+	wire [7:0] output_stuff = { 2'b0, ~buttons, tos_good };
 
 	always @(*)
 		data_output = output_stuff[current_bit[2:0]];
@@ -117,7 +118,7 @@ module TOS_Detect(
 		tos_input_1a <= tos_input;
 	wire transition = tos_input ^ tos_input_1a;
 	
-	reg [3:0] lasttx = 0;
+	reg [4:0] lasttx = 0;
 	always @(posedge xtal) begin
 		if (transition) begin
 			if (lasttx < 2) /* Too soon! */
-- 
2.39.2