POSLink.v

   1 module POSLink(
   2         input xtal,
   3         input [3:0] tos_inputs_e2,
   4         input serial_e2,
   5         input [1:0] buttons,
   6         output tos_output,
   7         output reg data_output,
   8         output reg [3:0] anode = 4'hF,
   9         output reg [7:0] cathode = 8'hFF);
  10
  11         reg [3:0] tos_inputs_e;
  12         reg [3:0] tos_inputs;
  13         reg serial_e;
  14         reg serial;
  15
  16         wire [3:0] tos_good;
  17
  18         /* Synchronize inputs */
  19         always @(posedge xtal) begin
  20                 tos_inputs_e <= tos_inputs_e2;
  21                 tos_inputs <= tos_inputs_e;
  22                 serial_e <= serial_e2;
  23                 serial <= serial_e;
  24         end
  25
  26         wire [11:0] data;
  27         wire data_good;
  28
  29         reg [1:0] seg;
  30
  31         always @(*)
  32                 case (seg)
  33                 2'b00:  anode = 4'b0111;
  34                 2'b01:  anode = 4'b1011;
  35                 2'b10:  anode = 4'b1101;
  36                 2'b11:  anode = 4'b1110;
  37                 endcase
  38
  39         reg [1:0] tos_select;
  40
  41 wire [4:0] edge_counter;
  42         wire [3:0] current_bit;
  43
  44         assign tos_output = tos_inputs_e2[tos_select];
  45
  46         always @(*) begin
  47                 cathode = data[7:0];
  48                 seg = data[9:8];
  49                 tos_select = data[11:10];
  50         end
  51
  52         // Buttons are active-low, so invert them.
  53         wire [7:0] output_stuff = { 2'b0, ~buttons, tos_good };
  54
  55         always @(*)
  56                 data_output = output_stuff[current_bit[2:0]];
  57
  58         TOS_Detect detect[3:0](.xtal(xtal), .tos_input(tos_inputs), .tos_good(tos_good));
  59         POS_Serial serinput(.xtal(xtal), .serial(serial), .data_reg(data), .current_bit(current_bit), .data_good(data_good), .edge_counter(edge_counter));
  60 endmodule
  61
  62
  63 module POS_Serial(
  64         input xtal,
  65         input serial,
  66         output reg [11:0] data_reg = 0,
  67         output reg [3:0] current_bit = 0,
  68         output reg [4:0] edge_counter = 0,
  69         output reg data_good = 0);
  70
  71         reg serial_1a;
  72
  73         always @(posedge xtal)
  74                 serial_1a <= serial;
  75
  76         wire edge_detect = serial ^ serial_1a;
  77
  78
  79         always @(posedge xtal) begin
  80                 data_good <= 0;
  81
  82                 if (edge_detect) begin
  83                         if (edge_counter == 31) begin
  84                                 current_bit <= 0;
  85 //                              data_reg <= 0;
  86                         end else begin
  87                 //              data_reg[11:1] = data_reg[10:0];
  88                 //              data_reg[0] = (edge_counter > 20);
  89                                 data_reg[current_bit] <= ((edge_counter > 20) ? 1'b1 : 1'b0);
  90                                 if (current_bit == 11) begin
  91                                         current_bit <= 0;
  92                                 end else
  93                                         current_bit <= current_bit + 1;
  94                         end
  95
  96                         edge_counter <= 0;
  97                 end else begin
  98                         if (edge_counter != 31)
  99                                 edge_counter <= edge_counter + 1;
 100                 end
 101         end
 102 endmodule
 103
 104
 105 /* xtal: 25MHz (==40ns)
 106  * Minimum: 100ns
 107  *          2 cycles (80 ns)
 108  * Maximum: 1000ns
 109  *          25 cycles (we'll allow 30 = 1200ns for good measure)
 110  */
 111 module TOS_Detect(
 112         input xtal,
 113         input tos_input,
 114         output reg tos_good = 0);
 115
 116         reg tos_input_1a = 0;
 117         always @(posedge xtal)
 118                 tos_input_1a <= tos_input;
 119         wire transition = tos_input ^ tos_input_1a;
 120
 121         reg [4:0] lasttx = 0;
 122         always @(posedge xtal) begin
 123                 if (transition) begin
 124                         if (lasttx < 2) /* Too soon! */
 125                                 tos_good <= 0;
 126                         else if (lasttx > 30) /* Too late! */
 127                                 tos_good <= 0;
 128                         else /* OK by me. */
 129                                 tos_good <= 1;
 130                         lasttx <= 0;
 131                 end else begin
 132                         if (lasttx != 31)
 133                                 lasttx <= lasttx + 1;
 134                         else
 135                                 tos_good <= 0;
 136                 end
 137         end
 138 endmodule
 139