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93bedefa JW |
1 | module POSLink( |
2 | input xtal, | |
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3 | input [3:0] tos_inputs_e2, |
4 | input serial_e2, | |
5 | input [1:0] buttons, | |
6 | output tos_output, | |
7 | output reg data_output, | |
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8 | output reg [3:0] anode = 4'hF, |
9 | output reg [7:0] cathode = 8'hFF); | |
93bedefa | 10 | |
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11 | reg [3:0] tos_inputs_e; |
12 | reg [3:0] tos_inputs; | |
13 | reg serial_e; | |
14 | reg serial; | |
15 | ||
16 | wire [3:0] tos_good; | |
17 | ||
18 | /* Synchronize inputs */ | |
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19 | always @(posedge xtal) begin |
20 | tos_inputs_e <= tos_inputs_e2; | |
21 | tos_inputs <= tos_inputs_e; | |
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22 | serial_e <= serial_e2; |
23 | serial <= serial_e; | |
93bedefa | 24 | end |
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25 | |
26 | wire [11:0] data; | |
27 | wire data_good; | |
28 | ||
29 | reg [1:0] seg; | |
30 | ||
31 | always @(*) | |
32 | case (seg) | |
33 | 2'b00: anode = 4'b0111; | |
34 | 2'b01: anode = 4'b1011; | |
35 | 2'b10: anode = 4'b1101; | |
36 | 2'b11: anode = 4'b1110; | |
37 | endcase | |
38 | ||
39 | reg [1:0] tos_select; | |
40 | ||
0170e492 | 41 | wire [4:0] edge_counter; |
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42 | wire [3:0] current_bit; |
43 | ||
44 | assign tos_output = tos_inputs_e2[tos_select]; | |
45 | ||
93bedefa | 46 | always @(*) begin |
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47 | cathode = data[7:0]; |
48 | seg = data[9:8]; | |
49 | tos_select = data[11:10]; | |
93bedefa | 50 | end |
0170e492 | 51 | |
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52 | // Buttons are active-low, so invert them. |
53 | wire [7:0] output_stuff = { 2'b0, ~buttons, tos_good }; | |
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54 | |
55 | always @(*) | |
56 | data_output = output_stuff[current_bit[2:0]]; | |
57 | ||
58 | TOS_Detect detect[3:0](.xtal(xtal), .tos_input(tos_inputs), .tos_good(tos_good)); | |
0170e492 | 59 | POS_Serial serinput(.xtal(xtal), .serial(serial), .data_reg(data), .current_bit(current_bit), .data_good(data_good), .edge_counter(edge_counter)); |
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60 | endmodule |
61 | ||
62 | ||
63 | module POS_Serial( | |
64 | input xtal, | |
65 | input serial, | |
66 | output reg [11:0] data_reg = 0, | |
67 | output reg [3:0] current_bit = 0, | |
0170e492 | 68 | output reg [4:0] edge_counter = 0, |
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69 | output reg data_good = 0); |
70 | ||
71 | reg serial_1a; | |
72 | ||
73 | always @(posedge xtal) | |
0170e492 | 74 | serial_1a <= serial; |
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75 | |
76 | wire edge_detect = serial ^ serial_1a; | |
77 | ||
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78 | |
79 | always @(posedge xtal) begin | |
0170e492 | 80 | data_good <= 0; |
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81 | |
82 | if (edge_detect) begin | |
83 | if (edge_counter == 31) begin | |
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84 | current_bit <= 0; |
85 | // data_reg <= 0; | |
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86 | end else begin |
87 | // data_reg[11:1] = data_reg[10:0]; | |
88 | // data_reg[0] = (edge_counter > 20); | |
0170e492 | 89 | data_reg[current_bit] <= ((edge_counter > 20) ? 1'b1 : 1'b0); |
23b3490b | 90 | if (current_bit == 11) begin |
0170e492 | 91 | current_bit <= 0; |
23b3490b | 92 | end else |
0170e492 | 93 | current_bit <= current_bit + 1; |
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94 | end |
95 | ||
0170e492 | 96 | edge_counter <= 0; |
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97 | end else begin |
98 | if (edge_counter != 31) | |
0170e492 | 99 | edge_counter <= edge_counter + 1; |
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100 | end |
101 | end | |
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102 | endmodule |
103 | ||
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104 | |
105 | /* xtal: 25MHz (==40ns) | |
106 | * Minimum: 100ns | |
107 | * 2 cycles (80 ns) | |
108 | * Maximum: 1000ns | |
109 | * 25 cycles (we'll allow 30 = 1200ns for good measure) | |
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110 | */ |
111 | module TOS_Detect( | |
112 | input xtal, | |
113 | input tos_input, | |
114 | output reg tos_good = 0); | |
115 | ||
116 | reg tos_input_1a = 0; | |
117 | always @(posedge xtal) | |
118 | tos_input_1a <= tos_input; | |
119 | wire transition = tos_input ^ tos_input_1a; | |
120 | ||
d3889785 | 121 | reg [4:0] lasttx = 0; |
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122 | always @(posedge xtal) begin |
123 | if (transition) begin | |
23b3490b | 124 | if (lasttx < 2) /* Too soon! */ |
93bedefa | 125 | tos_good <= 0; |
23b3490b | 126 | else if (lasttx > 30) /* Too late! */ |
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127 | tos_good <= 0; |
128 | else /* OK by me. */ | |
129 | tos_good <= 1; | |
130 | lasttx <= 0; | |
131 | end else begin | |
23b3490b | 132 | if (lasttx != 31) |
93bedefa JW |
133 | lasttx <= lasttx + 1; |
134 | else | |
135 | tos_good <= 0; | |
136 | end | |
137 | end | |
138 | endmodule | |
23b3490b | 139 |