X-Git-Url: http://git.joshuawise.com/netwatch.git/blobdiff_plain/81148fa15713ee68be49610206526d0725a5868f..d5d3737996d3828397e02f0f953fbc5c9e63f709:/ich2/smram-ich2.c?ds=inline

diff --git a/ich2/smram-ich2.c b/ich2/smram-ich2.c
index 20c2b8a..36e750f 100644
--- a/ich2/smram-ich2.c
+++ b/ich2/smram-ich2.c
@@ -1,9 +1,18 @@
+/* ich2-timer.c
+ * SMRAM access utility for ICH2 chipset
+ * NetWatch system management mode administration console
+ *
+ * Copyright (c) 2008 Jacob Potter and Joshua Wise.  All rights reserved.
+ * This program is free software; you can redistribute and/or modify it under
+ * the terms found in the file LICENSE in the root of this source tree. 
+ *
+ */
+
+
 #include "reg-82815.h"
 #include <pci.h>
 #include <smram.h>
 
-#ifdef __linux__
-
 static unsigned long memsz[] = {
 	0,			// 0
 	32*1024*1024,		// 1
@@ -23,6 +32,44 @@ static unsigned long memsz[] = {
 	512*1024*1024		// F
 };
 
+unsigned int smram_tseg_length(void) {
+	unsigned char smramc;
+	int usmm;
+
+	smramc = pci_read8(0, 0, 0, SMRAMC);
+
+	usmm = (smramc >> 4) & 0x3;
+
+	switch (usmm)
+	{
+	case 0:
+		return 0;
+	case 1:
+		return 0;
+	case 2:
+		return 512 * 1024;
+	case 3:
+		return 1024 * 1024;
+	}
+	return 0;
+}
+	
+void * smram_tseg_start(void) {
+	unsigned char drp, drp2;
+	unsigned int tom = 0;
+
+	drp = pci_read8(0, 0, 0, DRP);
+	drp2 = pci_read8(0, 0, 0, DRP2);
+
+	tom += memsz[drp & 0xF];
+	tom += memsz[drp >> 4];
+	tom += memsz[drp2 & 0xF];
+
+	return (void *)(tom - smram_tseg_length());
+}
+
+#ifndef __RAW__
+
 void smram_aseg_dump(void) {
 
 	unsigned char smramc, drp, drp2;
@@ -94,7 +141,7 @@ smram_state_t smram_save_state()
 
 void smram_restore_state(smram_state_t state)
 {
-	return pci_write8(0, 0, 0, SMRAMC, state); 
+	pci_write8(0, 0, 0, SMRAMC, state); 
 }
 
 int smram_aseg_set_state (int open) {
@@ -127,3 +174,25 @@ int smram_aseg_set_state (int open) {
 
 	return 0;
 }
+
+int smram_tseg_set_state (int open) {
+	unsigned char smramc;
+
+	if (smram_locked())
+		return -1;
+		
+	smramc = pci_read8(0, 0, 0, SMRAMC);
+
+	switch (open)
+	{
+	case SMRAM_TSEG_OPEN:
+		smramc = (smramc & 0x8F) | 0x00;
+		break;
+	default:
+		return -1;
+	}
+
+	pci_write8(0, 0, 0, SMRAMC, smramc);
+
+	return 0;
+}