X-Git-Url: http://git.joshuawise.com/netwatch.git/blobdiff_plain/07d1dd26f38ed450a9333741337e8091b37b4fc2..6093edb55a1c35ac1163e244f02023345e3e3aca:/ich2/smi.c

diff --git a/ich2/smi.c b/ich2/smi.c
index d255615..8865eab 100644
--- a/ich2/smi.c
+++ b/ich2/smi.c
@@ -1,3 +1,14 @@
+/* smi.c
+ * System management interrupt dispatch routines for ICH2 southbridge
+ * NetWatch system management mode administration console
+ *
+ * Copyright (c) 2008 Jacob Potter and Joshua Wise.  All rights reserved.
+ * This program is free software; you can redistribute and/or modify it under
+ * the terms found in the file LICENSE in the root of this source tree. 
+ *
+ */
+
+
 #include <smi.h>
 #include <pci.h>
 #include <io.h>
@@ -42,7 +53,10 @@ void smi_poll()
 	
 	if (sts & ICH2_SMI_STS_BIOS_STS)
 	{
-		output("Unhandled: BIOS_STS");
+		if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
+			output("Unhandled: BIOS_STS");
+		else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
+			_handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
 		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
 	}
 	
@@ -87,7 +101,10 @@ void smi_poll()
 		
 		if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
 		{
-			output("Unhandled: PM1_STS: PWRBTN_STS");
+			if (_handlers[SMI_EVENT_PWRBTN] == SMI_HANDLER_NONE)
+				output("Unhandled: PM1_STS: PWRBTN_STS");
+			else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
+				_handlers[SMI_EVENT_PWRBTN](SMI_EVENT_PWRBTN);
 			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
 		}
 		
@@ -129,6 +146,21 @@ void smi_poll()
 		unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 		unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 		unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
+		
+		if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
+		{
+			if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
+				output("Unhandled: DEVACT_KBC_ACT_STS");
+			else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
+				_handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
+			outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
+		}
+		
+		/* Refresh register cache so that we can print unhandleds as needed. */
+		mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
+		devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
+		devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
+		
 		if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
 			outputf("Unhandled: MON_SMI (%04x)", mon_smi);
 		if (devact_sts & devtrap_en)
@@ -185,6 +217,21 @@ int smi_enable_event(smi_event_t ev)
 			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 				ICH2_SMI_EN_SWSMI_TMR_EN);
 		return 0;
+	case SMI_EVENT_DEVTRAP_KBC:
+		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
+			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
+				ICH2_DEVTRAP_EN_KBC_TRP_EN);
+		return 0;
+	case SMI_EVENT_GBL_RLS:
+		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
+			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
+				ICH2_SMI_EN_BIOS_EN);
+		return 0;
+	case SMI_EVENT_PWRBTN:
+		outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
+			inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) |
+				ICH2_PM1_EN_PWRBTN_EN);
+		return 0;
 	default:
 		return -1;
 	}
@@ -199,6 +246,21 @@ int smi_disable_event(smi_event_t ev)
 			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 				~ICH2_SMI_EN_SWSMI_TMR_EN);
 		return 0;
+	case SMI_EVENT_DEVTRAP_KBC:
+		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
+			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
+				~ICH2_DEVTRAP_EN_KBC_TRP_EN);
+		return 0;
+	case SMI_EVENT_GBL_RLS:
+		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
+			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
+				~ICH2_SMI_EN_BIOS_EN);
+		return 0;
+	case SMI_EVENT_PWRBTN:
+		outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
+			inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) &
+				~ICH2_PM1_EN_PWRBTN_EN);
+		return 0;
 	default:
 		return -1;
 	}