Joshua Wise's Git repositories - netwatch.git/blob

1 /*

2 * 3c90x.c

3 * NetWatch

4 *

5 * A ring buffer-based, bus-mastering Ethernet driver.

6 *

7 * Derived from Etherboot's 3c90x.c, which is

10 *

11 * This program may be re-distributed in source or binary form, modified,

12 * sold, or copied for any purpose, provided that the above copyright message

13 * and this text are included with all source copies or derivative works, and

14 * provided that the above copyright message and this text are included in the

15 * documentation of any binary-only distributions. This program is distributed

16 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR

17 * PURPOSE or MERCHANTABILITY. Please read the associated documentation

18 * "3c90x.txt" before compiling and using this driver.

19 *

20 * REVISION HISTORY:

21 *

22 * v0.10 1-26-1998 GRB Initial implementation.

23 * v0.90 1-27-1998 GRB System works.

24 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.

25 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)

26 * Re-wrote poll and transmit for

27 * better error recovery and heavy

28 * network traffic operation

29 * v2.01 5-26-2003 NN Fixed driver alignment issue which

30 * caused system lockups if driver structures

31 * not 8-byte aligned.

32 * NetWatch0 12-07-2008 JAW Taken out back and shot.

33 *

34 */

35

36 #include "etherboot-compat.h"

37 #include "net.h"

38 #include <timer.h>

39 #include <io.h>

40 #include <pci.h>

41 #include <pci-bother.h>

42 #include <minilib.h>

43 #include <output.h>

44 #include <paging.h>

45

46 #define XCVR_MAGIC (0x5A00)

47

48 /*** Register definitions for the 3c905 ***/

49 enum Registers

50 {

51 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/

52 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/

53 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/

54 regDebugControl_w = 0x74, /** 905B Revision Only **/

55 regDebugData_l = 0x70, /** 905B Revision Only **/

56 regRealTimeCnt_l = 0x40, /** Universal **/

57 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/

58 regUpPoll_b = 0x3d, /** 905B Revision Only **/

59 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/

60 regUpListPtr_l = 0x38, /** Universal **/

61 regCountdown_w = 0x36, /** Universal **/

62 regFreeTimer_w = 0x34, /** Universal **/

63 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/

64 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/

65 regDnPoll_b = 0x2d, /** 905B Revision Only **/

66 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/

67 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/

68 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/

69 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/

70 /** **/

71 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/

72 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/

73 regTimer_b = 0x1a, /** Universal **/

74 regTxPktId_b = 0x18, /** 905B Revision Only **/

75 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/

76 };

77

78 /** following are windowed registers **/

79 enum Registers7

80 {

81 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/

82 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/

83 regVlanMask_7_w = 0x00, /** 905B Revision Only **/

84 };

85

86 enum Registers6

87 {

88 regBytesXmittedOk_6_w = 0x0c, /** Universal **/

89 regBytesRcvdOk_6_w = 0x0a, /** Universal **/

90 regUpperFramesOk_6_b = 0x09, /** Universal **/

91 regFramesDeferred_6_b = 0x08, /** Universal **/

92 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/

93 regFramesXmittedOk_6_b = 0x06, /** Universal **/

94 regRxOverruns_6_b = 0x05, /** Universal **/

95 regLateCollisions_6_b = 0x04, /** Universal **/

96 regSingleCollisions_6_b = 0x03, /** Universal **/

97 regMultipleCollisions_6_b = 0x02, /** Universal **/

98 regSqeErrors_6_b = 0x01, /** Universal **/

99 regCarrierLost_6_b = 0x00, /** Universal **/

100 };

101

102 enum Registers5

103 {

104 regIndicationEnable_5_w = 0x0c, /** Universal **/

105 regInterruptEnable_5_w = 0x0a, /** Universal **/

106 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/

107 regRxFilter_5_b = 0x08, /** Universal **/

108 regRxEarlyThresh_5_w = 0x06, /** Universal **/

109 regTxStartThresh_5_w = 0x00, /** Universal **/

110 };

111

112 enum Registers4

113 {

114 regUpperBytesOk_4_b = 0x0d, /** Universal **/

115 regBadSSD_4_b = 0x0c, /** Universal **/

116 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/

117 regPhysicalMgmt_4_w = 0x08, /** Universal **/

118 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/

119 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/

120 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/

121 };

122

123 enum Registers3

124 {

125 regTxFree_3_w = 0x0c, /** Universal **/

126 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/

127 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/

128 /** Reset Options on Non-B Revision **/

129 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/

130 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/

131 regInternalConfig_3_l = 0x00, /** Universal, different bit **/

132 /** definitions, pg 59 **/

133 };

134

135 enum Registers2

136 {

137 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/

138 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/

139 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/

140 };

141

142 enum Registers1

143 {

144 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/

145 };

146

147 enum Registers0

148 {

149 regEepromData_0_w = 0x0c, /** Universal **/

150 regEepromCommand_0_w = 0x0a, /** Universal **/

151 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/

152 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/

153 };

154

155

156 /*** The names for the eight register windows ***/

157 enum Windows

158 {

159 winPowerVlan7 = 0x07,

160 winStatistics6 = 0x06,

161 winTxRxControl5 = 0x05,

162 winDiagnostics4 = 0x04,

163 winTxRxOptions3 = 0x03,

164 winAddressing2 = 0x02,

165 winUnused1 = 0x01,

166 winEepromBios0 = 0x00,

167 };

168

169

170 /*** Command definitions for the 3c90X ***/

171 enum Commands

172 {

173 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/

174 cmdSelectRegisterWindow = 0x01, /** Universal **/

175 cmdEnableDcConverter = 0x02, /** **/

176 cmdRxDisable = 0x03, /** **/

177 cmdRxEnable = 0x04, /** Universal **/

178 cmdRxReset = 0x05, /** Universal **/

179 cmdStallCtl = 0x06, /** Universal **/

180 cmdTxEnable = 0x09, /** Universal **/

181 cmdTxDisable = 0x0A, /** **/

182 cmdTxReset = 0x0B, /** Universal **/

183 cmdRequestInterrupt = 0x0C, /** **/

184 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/

185 cmdSetInterruptEnable = 0x0E, /** Universal **/

186 cmdSetIndicationEnable = 0x0F, /** Universal **/

187 cmdSetRxFilter = 0x10, /** Universal **/

188 cmdSetRxEarlyThresh = 0x11, /** **/

189 cmdSetTxStartThresh = 0x13, /** **/

190 cmdStatisticsEnable = 0x15, /** **/

191 cmdStatisticsDisable = 0x16, /** **/

192 cmdDisableDcConverter = 0x17, /** **/

193 cmdSetTxReclaimThresh = 0x18, /** **/

194 cmdSetHashFilterBit = 0x19, /** **/

195 };

196

197

198 /*** Values for int status register bitmask **/

199 #define INT_INTERRUPTLATCH (1<<0)

200 #define INT_HOSTERROR (1<<1)

201 #define INT_TXCOMPLETE (1<<2)

202 #define INT_RXCOMPLETE (1<<4)

203 #define INT_RXEARLY (1<<5)

204 #define INT_INTREQUESTED (1<<6)

205 #define INT_UPDATESTATS (1<<7)

206 #define INT_LINKEVENT (1<<8)

207 #define INT_DNCOMPLETE (1<<9)

208 #define INT_UPCOMPLETE (1<<10)

209 #define INT_CMDINPROGRESS (1<<12)

210 #define INT_WINDOWNUMBER (7<<13)

211

212 /* These structures are all 64-bit aligned, as needed for bus-mastering I/O. */

213 typedef struct {

214 unsigned int addr;

215 unsigned int len;

216 } segment_t __attribute__ ((aligned(8)));

217

218 typedef struct {

219 unsigned int next;

220 unsigned int hdr;

221 segment_t segments[64 /* XXX magic */];

222 } txdesc_t __attribute__ ((aligned(8)));

223

224 /*** RX descriptor ***/

225 typedef struct {

226 unsigned int next;

227 unsigned int status;

228 segment_t segments[64];

229 } rxdesc_t __attribute__ ((aligned(8)));

230

231 typedef struct {

232 struct nic nic;

233 int is3c556;

234 int isBrev;

235 int curwnd;

236 int ioaddr;

237 } nic_3c90x_t;

238

239 static nic_3c90x_t _nic;

240

241 #define _inb(n,a) (inb((n)->ioaddr + (a)))

242 #define _inw(n,a) (inw((n)->ioaddr + (a)))

243 #define _inl(n,a) (inl((n)->ioaddr + (a)))

244

245 #define _outb(n,a,d) (outb((n)->ioaddr + (a), (d)))

246 #define _outw(n,a,d) (outw((n)->ioaddr + (a), (d)))

247 #define _outl(n,a,d) (outl((n)->ioaddr + (a), (d)))

248

249

250 static int _issue_command(nic_3c90x_t *nic, int cmd, int param)

251 {

252 _outw(nic, regCommandIntStatus_w, (cmd << 11) | param);

253

254 while (_inw(nic, regCommandIntStatus_w) & INT_CMDINPROGRESS)

255 ;

256

257 return 0;

258 }

259

260

261 /*** a3c90x_internal_SetWindow: selects a register window set.

262 ***/

263 static int _set_window(nic_3c90x_t *nic, int window)

264 {

265 if (nic->curwnd == window)

266 return 0;

267

268 _issue_command(nic, cmdSelectRegisterWindow, window);

269 nic->curwnd = window;

270

271 return 0;

272 }

273

274

275 /*** _read_eeprom - read data from the serial eeprom.

276 ***/

277 static unsigned short

278 _read_eeprom(nic_3c90x_t *nic, int address)

279 {

280 unsigned short val;

281

282 /** Select correct window **/

283 _set_window(nic, winEepromBios0);

284

285 /** Make sure the eeprom isn't busy **/

286 do

287 {

288 int i;

289 for (i = 0; i < 165; i++)

290 inb(0x80); /* wait 165 usec */

291 }

292 while(0x8000 & _inw(nic, regEepromCommand_0_w));

293

294 /** Read the value. **/

295 if (nic->is3c556)

296 _outw(nic, regEepromCommand_0_w, address + 0x230);

297 else

298 _outw(nic, regEepromCommand_0_w, address + 0x80);

299

300 do

301 {

302 int i;

303 for (i = 0; i < 165; i++)

304 inb(0x80); /* wait 165 usec */

305 }

306 while(0x8000 & _inw(nic, regEepromCommand_0_w));

307 val = _inw(nic, regEepromData_0_w);

308

309 return val;

310 }

311

312

313 #if 0

314 /*** a3c90x_reset: exported function that resets the card to its default

315 *** state. This is so the Linux driver can re-set the card up the way

316 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will

317 *** not alter the selected transceiver that we used to download the boot

318 *** image.

319 ***/

320 static void _reset(nic_3c90x_t *nic)

321 {

322 /** Send the reset command to the card **/

323 outputf("3c90x: issuing RESET");

324 _issue_command(nic, cmdGlobalReset, 0);

325

326 /** global reset command resets station mask, non-B revision cards

327 ** require explicit reset of values

328 **/

329 _set_window(nic, winAddressing2);

330 _outw(nic, regStationMask_2_3w+0, 0);

331 _outw(nic, regStationMask_2_3w+2, 0);

332 _outw(nic, regStationMask_2_3w+4, 0);

333

334 /** Issue transmit reset, wait for command completion **/

335 _issue_command(nic, cmdTxReset, 0);

336 if (!nic->isBrev)

337 _outb(nic, regTxFreeThresh_b, 0x01);

338 _issue_command(nic, cmdTxEnable, 0);

339

340 /**

341 ** reset of the receiver on B-revision cards re-negotiates the link

342 ** takes several seconds (a computer eternity)

343 **/

344 if (nic->isBrev)

345 _issue_command(nic, cmdRxReset, 0x04);

346 else

347 _issue_command(nic, cmdRxReset, 0x00);

348 _issue_command(nic, cmdRxEnable, 0);

349

350 _issue_command(nic, cmdSetInterruptEnable, 0);

351 /** enable rxComplete and txComplete **/

352 _issue_command(nic, cmdSetIndicationEnable, 0x0014);

353 /** acknowledge any pending status flags **/

354 _issue_command(nic, cmdAcknowledgeInterrupt, 0x661);

355

356 return;

357 }

358 #endif

359

360 /***************************** Transmit routines *****************************/

361

362 #define XMIT_BUFS 8

363

364 static txdesc_t txdescs[XMIT_BUFS];

365 static struct pbuf *txpbufs[XMIT_BUFS] = {0,};

366

367 /* txcons is the index into the ring buffer of the last packet that the

368 * 3c90x was seen processing, or -1 if the 3c90x was idle.

369 */

370 static int txcons = -1;

371

372 /* txprod is the index of the _next_ buffer that the driver will write into. */

373 static int txprod = 0;

374

375 /* _transmit adds a packet to the transmit ring buffer. If no space is

376 * available in the buffer, then _transmit blocks until a packet has been

377 * transmitted.

378 */

379 static void _transmit(struct nic *_nic, struct pbuf *p)

380 {

381 nic_3c90x_t *nic = (nic_3c90x_t *)_nic;

382 unsigned char status;

383 int len, n;

384

385 /* Wait for there to be space. */

386 if (txcons == txprod)

387 {

388 int i = 0;

389

390 outputf("3c90x: txbuf full, waiting for space...");

391 while (_inl(nic, regDnListPtr_l) != 0)

392 i++;

393 outputf("3c90x: took %d iters", i);

394 }

395

396 /* Stall the download engine so it doesn't bother us. */

397 _issue_command(nic, cmdStallCtl, 2 /* Stall download */);

398

399 /* Clean up old txcons. */

400 if (txcons != -1)

401 {

402 unsigned long curp = _inl(nic, regDnListPtr_l);

403 int end;

404

405 if (curp == 0)

406 end = txprod;

407 else

408 end = (curp - v2p(txdescs)) / sizeof(txdescs[0]);

409

410 while (txcons != end)

411 {

412 pbuf_free(txpbufs[txcons]);

413 txpbufs[txcons] = NULL;

414 txdescs[txcons].hdr = 0;

415 txdescs[txcons].next = 0;

416 txcons = (txcons + 1) % XMIT_BUFS;

417 }

418 if (txcons == txprod)

419 txcons = -1;

420 }

421

422 /* Look at the TX status */

423 status = _inb(nic, regTxStatus_b);

424 if (status)

425 {

426 outputf("3c90x: error: the nus.");

427 _outb(nic, regTxStatus_b, 0x00);

428 }

429

430 /* Set up the new txdesc. */

431 txdescs[txprod].next = 0;

432 len = 0;

433 n = 0;

434 txpbufs[txprod] = p;

435 pbuf_ref(p);

436 for (; p; p = p->next)

437 {

438 txdescs[txprod].segments[n].addr = v2p(p->payload);

439 txdescs[txprod].segments[n].len = p->len | (p->next ? 0 : (1 << 31));

440 len += p->len;

441 n++;

442 }

443 txdescs[txprod].hdr = len; /* If we wanted completion notification, bit 15 */

444

445 /* Now link the new one in, after it's been set up. */

446 txdescs[(txprod + XMIT_BUFS - 1) % XMIT_BUFS].next = v2p(&(txdescs[txprod]));

447

448 /* If the card is stopped, start it up again. */

449 if (_inl(nic, regDnListPtr_l) == 0)

450 {

451 _outl(nic, regDnListPtr_l, v2p(&(txdescs[txprod])));

452 txcons = txprod;

453 }

454

455 txprod = (txprod + 1) % XMIT_BUFS;

456

457 /* And let it proceed on its way. */

458 _issue_command(nic, cmdStallCtl, 3 /* Unstall download */);

459

460 #if 0

461 /** successful completion (sans "interrupt Requested" bit) **/

462 if ((status & 0xbf) == 0x80)

463 return;

464

465 outputf("3c90x: Status (%hhX)", status);

466 /** check error codes **/

467 if (status & 0x02)

468 {

469 outputf("3c90x: Tx Reclaim Error (%hhX)", status);

470 _reset(nic);

471 } else if (status & 0x04) {

472 outputf("3c90x: Tx Status Overflow (%hhX)", status);

473 for (i=0; i<32; i++)

474 _outb(nic, regTxStatus_b, 0x00);

475 /** must re-enable after max collisions before re-issuing tx **/

476 _issue_command(nic, cmdTxEnable, 0);

477 } else if (status & 0x08) {

478 outputf("3c90x: Tx Max Collisions (%hhX)", status);

479 /** must re-enable after max collisions before re-issuing tx **/

480 _issue_command(nic, cmdTxEnable, 0);

481 } else if (status & 0x10) {

482 outputf("3c90x: Tx Underrun (%hhX)", status);

483 _reset(nic);

484 } else if (status & 0x20) {

485 outputf("3c90x: Tx Jabber (%hhX)", status);

486 _reset(nic);

487 } else if ((status & 0x80) != 0x80) {

488 outputf("3c90x: Internal Error - Incomplete Transmission (%hhX)", status);

489 _reset(nic);

490 }

491 #endif

492 }

493

494 /***************************** Receive routines *****************************/

495 #define MAX_RECV_SIZE 1536

496 #define RECV_BUFS 32

497

498 static rxdesc_t rxdescs[RECV_BUFS];

499 static struct pbuf *rxpbufs[RECV_BUFS] = {0,};

500

501 /* rxcons is the pointer to the receive descriptor that the ethernet card will

502 * write into next.

503 */

504 static int rxcons = 0;

505

506 /* rxprod is the pointer to the receive descriptor that the driver will

507 * allocate next.

508 */

509 static int rxprod = 0;

510

511 /* _recv_prepare fills the 3c90x's ring buffer with fresh pbufs from lwIP.

512 * The upload engine need not be stalled.

513 */

514 static void _recv_prepare(nic_3c90x_t *nic)

515 {

516 int oldprod;

517

518 oldprod = rxprod;

519 while ((rxprod != rxcons) || !rxpbufs[rxprod])

520 {

521 int i;

522 struct pbuf *p;

523

524 if (!rxpbufs[rxprod])

525 rxpbufs[rxprod] = p = pbuf_alloc(PBUF_RAW, MAX_RECV_SIZE, PBUF_POOL);

526 else {

527 outputf("WARNING: 3c90x has pbuf in slot %d", rxprod);

528 p = rxpbufs[rxprod];

529 }

530

531 if (!p)

532 {

533 outputf("3c90x: out of memory for rx pbuf?");

534 break;

535 }

536

537 rxdescs[rxprod].status = 0;

538 rxdescs[rxprod].next = 0;

539 for (i = 0; p; p = p->next, i++)

540 {

541 rxdescs[rxprod].segments[i].addr = v2p(p->payload);

542 rxdescs[rxprod].segments[i].len = p->len | (p->next ? 0 : (1 << 31));

543 }

544

545 /* Hook in the new one after and only after it's been fully set up. */

546 rxdescs[(rxprod + RECV_BUFS - 1) % RECV_BUFS].next = v2p(&(rxdescs[rxprod]));

547 rxprod = (rxprod + 1) % RECV_BUFS;

548 }

549

550 if (_inl(nic, regUpListPtr_l) == 0 && rxpbufs[oldprod]) /* Ran out of shit, and got new shit? */

551 {

552 _outl(nic, regUpListPtr_l, v2p(&rxdescs[oldprod]));

553 outputf("3c90x: WARNING: Ran out of rx slots");

554 }

555

556 _issue_command(nic, cmdStallCtl, 1 /* Unstall upload */);

557 }

558

559 /* _recv polls the ring buffer to see if any packets are available. If any

560 * are, then eth_recv is called for each available. _recv returns how many

561 * packets it received successfully. Whether _recv got any packets or not,

562 * _recv does not block, and reinitializes the ring buffer with fresh pbufs.

563 */

564 static int _recv(struct nic *_nic)

565 {

566 nic_3c90x_t *nic = (nic_3c90x_t *)_nic;

567 int errcode, n = 0;

568 struct pbuf *p;

569

570 /* Nothing to do? */

571 while ((rxdescs[rxcons].status & ((1<<14) | (1<<15))) != 0)

572 {

573 /** Check for Error (else we have good packet) **/

574 if (rxdescs[rxcons].status & (1<<14))

575 {

576 errcode = rxdescs[rxcons].status;

577 if (errcode & (1<<16))

578 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);

579 else if (errcode & (1<<17))

580 outputf("3C90X: Runt Frame (%hX)",errcode>>16);

581 else if (errcode & (1<<18))

582 outputf("3C90X: Alignment Error (%hX)",errcode>>16);

583 else if (errcode & (1<<19))

584 outputf("3C90X: CRC Error (%hX)",errcode>>16);

585 else if (errcode & (1<<20))

586 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);

587 else

588 outputf("3C90X: Packet error (%hX)",errcode>>16);

589

590 p = NULL;

591 pbuf_free(rxpbufs[rxcons]); /* Bounce the old one before setting it up again. */

592 } else {

593 p = rxpbufs[rxcons];

594 pbuf_realloc(p, rxdescs[rxcons].status & 0x1FFF); /* Resize the packet to how large it actually is. */

595 }

596

597 rxpbufs[rxcons] = NULL;

598 rxdescs[rxcons].status = 0;

599 rxcons = (rxcons + 1) % RECV_BUFS;

600

601 if (p)

602 {

603 eth_recv(_nic, p);

604 n++;

605 }

606 }

607

608 _recv_prepare(nic); /* Light the NIC up again. */

609 return n;

610 }

611

612 /*** a3c90x_probe: exported routine to probe for the 3c905 card and perform

613 *** initialization. If this routine is called, the pci functions did find the

614 *** card. We just have to init it here.

615 ***/

616 static int _probe(struct pci_dev *pci, void *data)

617 {

618 nic_3c90x_t *nic = &_nic;

619 int i, c;

620 unsigned short eeprom[0x100];

621 unsigned int cfg;

622 unsigned int mopt;

623 unsigned int mstat;

624 unsigned short linktype;

625 #define HWADDR_OFFSET 10

626

627 unsigned long ioaddr = 0;

628 for (i = 0; i < 6; i++)

629 if (pci->bars[i].type == PCI_BAR_IO)

630 {

631 ioaddr = pci->bars[i].addr;

632 break;

633 }

634

635 if (ioaddr == 0)

636 {

637 outputf("3c90x: Unable to find I/O address");

638 return 0;

639 }

640

641 /* Power it on */

642 pci_write16(pci->bus, pci->dev, pci->fn, 0xE0,

643 pci_read16(pci->bus, pci->dev, pci->fn, 0xE0) & ~0x3);

644

645 outputf("3c90x: Picked I/O address %04x", ioaddr);

646 pci_bother_add(pci);

647 nic->nic.ioaddr = ioaddr & ~3;

648 nic->nic.irqno = 0;

649

650 nic->ioaddr = ioaddr;

651 nic->is3c556 = (pci->did == 0x6055);

652 nic->curwnd = 255;

653 switch (_read_eeprom(nic, 0x03))

654 {

655 case 0x9000: /** 10 Base TPO **/

656 case 0x9001: /** 10/100 T4 **/

657 case 0x9050: /** 10/100 TPO **/

658 case 0x9051: /** 10 Base Combo **/

659 nic->isBrev = 0;

660 break;

661

662 case 0x9004: /** 10 Base TPO **/

663 case 0x9005: /** 10 Base Combo **/

664 case 0x9006: /** 10 Base TPO and Base2 **/

665 case 0x900A: /** 10 Base FL **/

666 case 0x9055: /** 10/100 TPO **/

667 case 0x9056: /** 10/100 T4 **/

668 case 0x905A: /** 10 Base FX **/

669 default:

670 nic->isBrev = 1;

671 break;

672 }

673

674 /** Load the EEPROM contents **/

675 if (nic->isBrev)

676 for(i=0;i<=0x20;i++)

677 eeprom[i] = _read_eeprom(nic, i);

678 else

679 for(i=0;i<=0x17;i++)

680 eeprom[i] = _read_eeprom(nic, i);

681

682 /** Retrieve the Hardware address and print it on the screen. **/

683 nic->nic.hwaddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;

684 nic->nic.hwaddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;

685 nic->nic.hwaddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;

686 nic->nic.hwaddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;

687 nic->nic.hwaddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;

688 nic->nic.hwaddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;

689 outputf("MAC Address = %02x:%02x:%02x:%02x:%02x:%02x",

690 nic->nic.hwaddr[0], nic->nic.hwaddr[1],

691 nic->nic.hwaddr[2], nic->nic.hwaddr[3],

692 nic->nic.hwaddr[4], nic->nic.hwaddr[5]);

693

694 /** 3C556: Invert MII power **/

695 if (nic->is3c556) {

696 _set_window(nic, winAddressing2);

697 _outw(nic, regResetOptions_2_w,

698 _inw(nic, regResetOptions_2_w) | 0x4000);

699 }

700

701 /* Test if the link is good; if not, bail out */

702 _set_window(nic, winDiagnostics4);

703 mstat = _inw(nic, regMediaStatus_4_w);

704 if((mstat & (1<<11)) == 0) {

705 outputf("3c90x: valid link not established");

706 return 0;

707 }

708

709 /* Program the MAC address into the station address registers */

710 _set_window(nic, winAddressing2);

711 _outw(nic, regStationAddress_2_3w, htons(eeprom[HWADDR_OFFSET + 0]));

712 _outw(nic, regStationAddress_2_3w+2, htons(eeprom[HWADDR_OFFSET + 1]));

713 _outw(nic, regStationAddress_2_3w+4, htons(eeprom[HWADDR_OFFSET + 2]));

714 _outw(nic, regStationMask_2_3w+0, 0);

715 _outw(nic, regStationMask_2_3w+2, 0);

716 _outw(nic, regStationMask_2_3w+4, 0);

717

718 /** Read the media options register, print a message and set default

719 ** xcvr.

720 **

721 ** Uses Media Option command on B revision, Reset Option on non-B

722 ** revision cards -- same register address

723 **/

724 _set_window(nic, winTxRxOptions3);

725 mopt = _inw(nic, regResetMediaOptions_3_w);

726

727 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/

728 if (!nic->isBrev)

729 mopt &= 0x7F;

730

731 outputf("3c90x: connectors present: ");

732 c = 0;

733 linktype = 0x0008;

734 if (mopt & 0x01)

735 {

736 outputf(" 100Base-T4");

737 linktype = 0x0006;

738 }

739 if (mopt & 0x04)

740 {

741 outputf(" 100Base-FX");

742 linktype = 0x0005;

743 }

744 if (mopt & 0x10)

745 {

746 outputf(" 10Base-2");

747 linktype = 0x0003;

748 }

749 if (mopt & 0x20)

750 {

751 outputf(" AUI");

752 linktype = 0x0001;

753 }

754 if (mopt & 0x40)

755 {

756 outputf(" MII");

757 linktype = 0x0006;

758 }

759 if ((mopt & 0xA) == 0xA)

760 {

761 outputf(" 10Base-T / 100Base-TX");

762 linktype = 0x0008;

763 } else if ((mopt & 0xA) == 0x2) {

764 outputf(" 100Base-TX");

765 linktype = 0x0008;

766 } else if ((mopt & 0xA) == 0x8) {

767 outputf(" 10Base-T");

768 linktype = 0x0008;

769 }

770

771 /** Determine transceiver type to use, depending on value stored in

772 ** eeprom 0x16

773 **/

774 if (nic->isBrev && ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC))

775 linktype = eeprom[0x16] & 0x000F; /* User-defined */

776 else if (linktype == 0x0009) {

777 if (nic->isBrev)

778 outputf("WARNING: MII External MAC Mode only supported on B-revision "

779 "cards!!!!\nFalling Back to MII Mode\n");

780 linktype = 0x0006;

781 }

782

783 /** enable DC converter for 10-Base-T **/

784 if (linktype == 0x0003)

785 _issue_command(nic, cmdEnableDcConverter, 0);

786

787 /** Set the link to the type we just determined. **/

788 _set_window(nic, winTxRxOptions3);

789 cfg = _inl(nic, regInternalConfig_3_l);

790 cfg &= ~(0xF<<20);

791 cfg |= (linktype<<20);

792 _outl(nic, regInternalConfig_3_l, cfg);

793

794 /* Reset and turn on the transmit engine. */

795 _issue_command(nic, cmdTxReset, 0);

796 if (!nic->isBrev)

797 _outb(nic, regTxFreeThresh_b, 0x01);

798 _issue_command(nic, cmdTxEnable, 0);

799

800 /* Reset and turn on the receive engine. */

801 _issue_command(nic, cmdRxReset, nic->isBrev ? 0x04 : 0x00);

802 _issue_command(nic, cmdSetRxFilter, 0x01 + 0x02 + 0x04); /* Individual, multicast, broadcast */

803 _recv_prepare(nic); /* Set up the ring buffer... */

804 _issue_command(nic, cmdRxEnable, 0); /* ... and light it up. */

805

806 /* Turn on interrupts, and ack any that are hanging out. */

807 _issue_command(nic, cmdSetInterruptEnable, 0);

808 _issue_command(nic, cmdSetIndicationEnable, 0x0014);

809 _issue_command(nic, cmdAcknowledgeInterrupt, 0x661);

810

811 /* Register with lwIP. */

812 nic->nic.recv = _recv;

813 nic->nic.transmit = _transmit;

814 eth_register(&(nic->nic));

815

816 return 1;

817 }

818

819 static struct pci_id _pci_ids[] = {

820 /* Original 90x revisions: */

821 PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */

822 PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */

823 PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */

824 PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */

825 PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */

826 /* Newer 90xB revisions: */

827 PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */

828 PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */

829 PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */

830 PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */

831 PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */

832 PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */

833 PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */

834 PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */

835 /* Newer 90xC revision: */

836 PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */

837 PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */

838 PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),

839 PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */

840 PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */

841 PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */

842 PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),

843 PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),

844 PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),

845 };

846

847 struct pci_driver a3c90x_driver = {

848 .name = "3c90x",

849 .probe = _probe,

850 .ids = _pci_ids,

851 .id_count = sizeof(_pci_ids)/sizeof(_pci_ids[0]),

852 };