ich2/smi.c

   1 /* smi.c
   2  * System management interrupt dispatch routines for ICH2 southbridge
   3  * NetWatch system management mode administration console
   4  *
   5  * Copyright (c) 2008 Jacob Potter and Joshua Wise.  All rights reserved.
   6  * This program is free software; you can redistribute and/or modify it under
   7  * the terms found in the file LICENSE in the root of this source tree.
   8  *
   9  */
  10
  11
  12 #include <smi.h>
  13 #include <pci.h>
  14 #include <io.h>
  15 #include <stdint.h>
  16 #include <vga-overlay.h>
  17 #include <reg-82801b.h>
  18 #include <output.h>
  19
  20 static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
  21
  22 static uint16_t _get_PMBASE()
  23 {
  24         static long pmbase = -1;
  25
  26         if (pmbase == -1)       /* Memoize it so that we don't have to hit PCI so often. */
  27                 pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
  28
  29         return pmbase;
  30 }
  31
  32 void smi_disable()
  33 {
  34         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  35         outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
  36 }
  37
  38 void smi_enable()
  39 {
  40         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  41         outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
  42 }
  43
  44 unsigned long smi_status()
  45 {
  46         unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
  47         return inl(smi_sts);
  48 }
  49
  50 void smi_poll()
  51 {
  52         unsigned long sts = smi_status();
  53
  54         if (sts & ICH2_SMI_STS_BIOS_STS)
  55         {
  56                 if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
  57                         output("Unhandled: BIOS_STS");
  58                 else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
  59                         _handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
  60                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
  61         }
  62
  63         if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
  64         {
  65                 output("Unhandled: LEGACY_USB_STS");
  66                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
  67         }
  68
  69         if (sts & ICH2_SMI_STS_SLP_SMI_STS)
  70         {
  71                 output("Unhandled: SLP_SMI_STS");
  72                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
  73         }
  74
  75         if (sts & ICH2_SMI_STS_APM_STS)
  76         {
  77                 output("Unhandled: APM_STS");
  78                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
  79         }
  80
  81         if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)   // Ack it, then request another.
  82         {
  83                 if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
  84                         output("Unhandled: SWSMI_TMR_STS");
  85                 else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
  86                         _handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
  87                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
  88         }
  89
  90         if (sts & ICH2_SMI_STS_PM1_STS_REG)
  91         {
  92                 unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
  93                 unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
  94
  95                 pm1_sts &= pm1_en;
  96                 if (pm1_sts & ICH2_PM1_STS_RTC_STS)
  97                 {
  98                         output("Unhandled: PM1_STS: RTC_STS");
  99                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
 100                 }
 101
 102                 if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
 103                 {
 104                         if (_handlers[SMI_EVENT_PWRBTN] == SMI_HANDLER_NONE)
 105                                 output("Unhandled: PM1_STS: PWRBTN_STS");
 106                         else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
 107                                 _handlers[SMI_EVENT_PWRBTN](SMI_EVENT_PWRBTN);
 108                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
 109                 }
 110
 111                 if (pm1_sts & ICH2_PM1_STS_GBL_STS)
 112                 {
 113                         output("Unhandled: PM1_STS: GBL_STS");
 114                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
 115                 }
 116
 117                 if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
 118                 {
 119                         output("Unhandled: PM1_STS: TMROF_STS");
 120                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
 121                 }
 122
 123                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
 124         }
 125
 126         if (sts & ICH2_SMI_STS_GPE0_STS)
 127         {
 128                 /* XXX -- trawl through GPE0_STS to see what happened */
 129                 output("XXX Unhandled: GPE0_STS (expect lockup)");
 130         }
 131
 132         if (sts & ICH2_SMI_STS_GPE1_STS)
 133         {
 134                 /* XXX -- trawl through GPE1_STS to see what happened */
 135                 output("XXX Unhandled: GPE1_STS (expect lockup)");
 136         }
 137
 138         if (sts & ICH2_SMI_STS_MCSMI_STS)
 139         {
 140                 output("Unhandled: MCSMI_STS");
 141                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
 142         }
 143
 144         if (sts & ICH2_SMI_STS_DEVMON_STS)
 145         {
 146                 unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 147                 unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 148                 unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 149
 150                 if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
 151                 {
 152                         if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
 153                                 output("Unhandled: DEVACT_KBC_ACT_STS");
 154                         else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
 155                                 _handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
 156                         outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
 157                 }
 158
 159                 /* Refresh register cache so that we can print unhandleds as needed. */
 160                 mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 161                 devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 162                 devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 163
 164                 if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
 165                         outputf("Unhandled: MON_SMI (%04x)", mon_smi);
 166                 if (devact_sts & devtrap_en)
 167                         outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
 168         }
 169
 170         if (sts & ICH2_SMI_STS_TCO_STS)
 171         {
 172                 output("Unhandled: TCO_STS");
 173                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
 174         }
 175
 176         if (sts & ICH2_SMI_STS_PERIODIC_STS)
 177         {
 178                 output("Unhandled: PERIODIC_STS");
 179                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
 180         }
 181
 182         if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
 183         {
 184                 output("Unhandled: SERIRQ_SMI_STS");
 185                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
 186         }
 187
 188         if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
 189         {
 190                 output("Unhandled: SMBUS_SMI_STS");
 191                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
 192         }
 193
 194         if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)   /* Either the chipset is buggy, or we are. */
 195                 outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
 196
 197         outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 198                 inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 199                         ICH2_SMI_EN_EOS |
 200                         ICH2_SMI_EN_GBL_SMI_EN);
 201 }
 202
 203 int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
 204 {
 205         if (ev >= SMI_EVENT_MAX)
 206                 return -1;
 207         _handlers[ev] = hnd;
 208         return 0;
 209 }
 210
 211 int smi_enable_event(smi_event_t ev)
 212 {
 213         switch(ev)
 214         {
 215         case SMI_EVENT_FAST_TIMER:
 216                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 217                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 218                                 ICH2_SMI_EN_SWSMI_TMR_EN);
 219                 return 0;
 220         case SMI_EVENT_DEVTRAP_KBC:
 221                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 222                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
 223                                 ICH2_DEVTRAP_EN_KBC_TRP_EN);
 224                 return 0;
 225         case SMI_EVENT_GBL_RLS:
 226                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 227                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 228                                 ICH2_SMI_EN_BIOS_EN);
 229                 return 0;
 230         case SMI_EVENT_PWRBTN:
 231                 outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
 232                         inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) |
 233                                 ICH2_PM1_EN_PWRBTN_EN);
 234                 return 0;
 235         default:
 236                 return -1;
 237         }
 238 }
 239
 240 int smi_disable_event(smi_event_t ev)
 241 {
 242         switch(ev)
 243         {
 244         case SMI_EVENT_FAST_TIMER:
 245                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 246                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 247                                 ~ICH2_SMI_EN_SWSMI_TMR_EN);
 248                 return 0;
 249         case SMI_EVENT_DEVTRAP_KBC:
 250                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 251                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
 252                                 ~ICH2_DEVTRAP_EN_KBC_TRP_EN);
 253                 return 0;
 254         case SMI_EVENT_GBL_RLS:
 255                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 256                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 257                                 ~ICH2_SMI_EN_BIOS_EN);
 258                 return 0;
 259         case SMI_EVENT_PWRBTN:
 260                 outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
 261                         inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) &
 262                                 ~ICH2_PM1_EN_PWRBTN_EN);
 263                 return 0;
 264         default:
 265                 return -1;
 266         }
 267 }