hardware/ich2/smi.c

   1 /* smi.c
   2  * System management interrupt dispatch routines for ICH2 southbridge
   3  * NetWatch system management mode administration console
   4  *
   5  * Copyright (c) 2008 Jacob Potter and Joshua Wise.  All rights reserved.
   6  * This program is free software; you can redistribute and/or modify it under
   7  * the terms found in the file LICENSE in the root of this source tree.
   8  *
   9  */
  10
  11
  12 #include <smi.h>
  13 #include <pci.h>
  14 #include <io.h>
  15 #include <stdint.h>
  16 #include <vga-overlay.h>
  17 #include <reg-82801b.h>
  18 #include <output.h>
  19
  20 static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
  21
  22 static uint16_t _get_PMBASE()
  23 {
  24         static long pmbase = -1;
  25
  26         if (pmbase == -1)       /* Memoize it so that we don't have to hit PCI so often. */
  27                 pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
  28
  29         return pmbase;
  30 }
  31
  32 void smi_disable()
  33 {
  34         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  35         outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
  36
  37         /* Try really hard to shut up USB_LEGKEY. */
  38         pci_write16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY, 0x0);
  39         pci_write16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY,
  40                 pci_read16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY));
  41         pci_write16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY, 0x0);
  42         pci_write16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY,
  43                 pci_read16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY));
  44
  45 }
  46
  47 void smi_enable()
  48 {
  49         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  50         outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
  51 }
  52
  53 unsigned long smi_status()
  54 {
  55         unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
  56         return inl(smi_sts);
  57 }
  58
  59 void smi_poll()
  60 {
  61         unsigned long sts = smi_status();
  62
  63         if (sts & ICH2_SMI_STS_BIOS_STS)
  64         {
  65                 if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
  66                         output("Unhandled: BIOS_STS");
  67                 else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
  68                         _handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
  69                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
  70         }
  71
  72         if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
  73         {
  74                 output("Unhandled: LEGACY_USB_STS");
  75                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
  76         }
  77
  78         if (sts & ICH2_SMI_STS_SLP_SMI_STS)
  79         {
  80                 output("Unhandled: SLP_SMI_STS");
  81                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
  82         }
  83
  84         if (sts & ICH2_SMI_STS_APM_STS)
  85         {
  86                 output("Unhandled: APM_STS");
  87                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
  88         }
  89
  90         if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)   // Ack it, then request another.
  91         {
  92                 if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
  93                         output("Unhandled: SWSMI_TMR_STS");
  94                 else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
  95                         _handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
  96                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
  97         }
  98
  99         if (sts & ICH2_SMI_STS_PM1_STS_REG)
 100         {
 101                 unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
 102                 unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
 103
 104                 pm1_sts &= pm1_en;
 105                 if (pm1_sts & ICH2_PM1_STS_RTC_STS)
 106                 {
 107                         output("Unhandled: PM1_STS: RTC_STS");
 108                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
 109                 }
 110
 111                 if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
 112                 {
 113                         if (_handlers[SMI_EVENT_PWRBTN] == SMI_HANDLER_NONE)
 114                                 output("Unhandled: PM1_STS: PWRBTN_STS");
 115                         else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
 116                                 _handlers[SMI_EVENT_PWRBTN](SMI_EVENT_PWRBTN);
 117                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
 118                 }
 119
 120                 if (pm1_sts & ICH2_PM1_STS_GBL_STS)
 121                 {
 122                         output("Unhandled: PM1_STS: GBL_STS");
 123                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
 124                 }
 125
 126                 if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
 127                 {
 128                         output("Unhandled: PM1_STS: TMROF_STS");
 129                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
 130                 }
 131
 132                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
 133         }
 134
 135         if (sts & ICH2_SMI_STS_GPE0_STS)
 136         {
 137                 /* XXX -- trawl through GPE0_STS to see what happened */
 138                 output("XXX Unhandled: GPE0_STS (expect lockup)");
 139         }
 140
 141         if (sts & ICH2_SMI_STS_GPE1_STS)
 142         {
 143                 /* XXX -- trawl through GPE1_STS to see what happened */
 144                 output("XXX Unhandled: GPE1_STS (expect lockup)");
 145         }
 146
 147         if (sts & ICH2_SMI_STS_MCSMI_STS)
 148         {
 149                 output("Unhandled: MCSMI_STS");
 150                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
 151         }
 152
 153         if (sts & ICH2_SMI_STS_DEVMON_STS)
 154         {
 155                 unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 156                 unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 157                 unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 158
 159                 if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
 160                 {
 161                         if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
 162                                 output("Unhandled: DEVACT_KBC_ACT_STS");
 163                         else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
 164                                 _handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
 165                         outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
 166                 }
 167
 168                 /* Refresh register cache so that we can print unhandleds as needed. */
 169                 mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 170                 devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 171                 devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 172
 173                 if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
 174                         outputf("Unhandled: MON_SMI (%04x)", mon_smi);
 175                 if (devact_sts & devtrap_en)
 176                         outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
 177         }
 178
 179         if (sts & ICH2_SMI_STS_TCO_STS)
 180         {
 181                 output("Unhandled: TCO_STS");
 182                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
 183         }
 184
 185         if (sts & ICH2_SMI_STS_PERIODIC_STS)
 186         {
 187                 output("Unhandled: PERIODIC_STS");
 188                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
 189         }
 190
 191         if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
 192         {
 193                 output("Unhandled: SERIRQ_SMI_STS");
 194                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
 195         }
 196
 197         if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
 198         {
 199                 output("Unhandled: SMBUS_SMI_STS");
 200                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
 201         }
 202
 203         if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)   /* Either the chipset is buggy, or we are. */
 204                 outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
 205
 206         outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 207                 inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 208                         ICH2_SMI_EN_EOS |
 209                         ICH2_SMI_EN_GBL_SMI_EN);
 210 }
 211
 212 int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
 213 {
 214         if (ev >= SMI_EVENT_MAX)
 215                 return -1;
 216         _handlers[ev] = hnd;
 217         return 0;
 218 }
 219
 220 int smi_enable_event(smi_event_t ev)
 221 {
 222         switch(ev)
 223         {
 224         case SMI_EVENT_FAST_TIMER:
 225                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 226                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 227                                 ICH2_SMI_EN_SWSMI_TMR_EN);
 228                 return 0;
 229         case SMI_EVENT_DEVTRAP_KBC:
 230                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 231                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
 232                                 ICH2_DEVTRAP_EN_KBC_TRP_EN);
 233                 return 0;
 234         case SMI_EVENT_GBL_RLS:
 235                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 236                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 237                                 ICH2_SMI_EN_BIOS_EN);
 238                 return 0;
 239         case SMI_EVENT_PWRBTN:
 240                 outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
 241                         inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) |
 242                                 ICH2_PM1_EN_PWRBTN_EN);
 243                 return 0;
 244         default:
 245                 return -1;
 246         }
 247 }
 248
 249 int smi_disable_event(smi_event_t ev)
 250 {
 251         switch(ev)
 252         {
 253         case SMI_EVENT_FAST_TIMER:
 254                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 255                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 256                                 ~ICH2_SMI_EN_SWSMI_TMR_EN);
 257                 return 0;
 258         case SMI_EVENT_DEVTRAP_KBC:
 259                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 260                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
 261                                 ~ICH2_DEVTRAP_EN_KBC_TRP_EN);
 262                 return 0;
 263         case SMI_EVENT_GBL_RLS:
 264                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 265                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 266                                 ~ICH2_SMI_EN_BIOS_EN);
 267                 return 0;
 268         case SMI_EVENT_PWRBTN:
 269                 outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
 270                         inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) &
 271                                 ~ICH2_PM1_EN_PWRBTN_EN);
 272                 return 0;
 273         default:
 274                 return -1;
 275         }
 276 }