ich2/smi.c

   1 #include <smi.h>
   2 #include <pci.h>
   3 #include <io.h>
   4 #include <stdint.h>
   5 #include <vga-overlay.h>
   6 #include <reg-82801b.h>
   7 #include <output.h>
   8
   9 static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
  10
  11 static uint16_t _get_PMBASE()
  12 {
  13         static long pmbase = -1;
  14
  15         if (pmbase == -1)       /* Memoize it so that we don't have to hit PCI so often. */
  16                 pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
  17
  18         return pmbase;
  19 }
  20
  21 void smi_disable()
  22 {
  23         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  24         outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
  25 }
  26
  27 void smi_enable()
  28 {
  29         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  30         outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
  31 }
  32
  33 unsigned long smi_status()
  34 {
  35         unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
  36         return inl(smi_sts);
  37 }
  38
  39 void smi_poll()
  40 {
  41         unsigned long sts = smi_status();
  42
  43         if (sts & ICH2_SMI_STS_BIOS_STS)
  44         {
  45                 output("Unhandled: BIOS_STS");
  46                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
  47         }
  48
  49         if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
  50         {
  51                 output("Unhandled: LEGACY_USB_STS");
  52                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
  53         }
  54
  55         if (sts & ICH2_SMI_STS_SLP_SMI_STS)
  56         {
  57                 output("Unhandled: SLP_SMI_STS");
  58                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
  59         }
  60
  61         if (sts & ICH2_SMI_STS_APM_STS)
  62         {
  63                 output("Unhandled: APM_STS");
  64                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
  65         }
  66
  67         if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)   // Ack it, then request another.
  68         {
  69                 if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
  70                         output("Unhandled: SWSMI_TMR_STS");
  71                 else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
  72                         _handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
  73                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
  74         }
  75
  76         if (sts & ICH2_SMI_STS_PM1_STS_REG)
  77         {
  78                 unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
  79                 unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
  80
  81                 pm1_sts &= pm1_en;
  82                 if (pm1_sts & ICH2_PM1_STS_RTC_STS)
  83                 {
  84                         output("Unhandled: PM1_STS: RTC_STS");
  85                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
  86                 }
  87
  88                 if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
  89                 {
  90                         output("Unhandled: PM1_STS: PWRBTN_STS");
  91                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
  92                 }
  93
  94                 if (pm1_sts & ICH2_PM1_STS_GBL_STS)
  95                 {
  96                         output("Unhandled: PM1_STS: GBL_STS");
  97                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
  98                 }
  99
 100                 if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
 101                 {
 102                         output("Unhandled: PM1_STS: TMROF_STS");
 103                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
 104                 }
 105
 106                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
 107         }
 108
 109         if (sts & ICH2_SMI_STS_GPE0_STS)
 110         {
 111                 /* XXX -- trawl through GPE0_STS to see what happened */
 112                 output("XXX Unhandled: GPE0_STS (expect lockup)");
 113         }
 114
 115         if (sts & ICH2_SMI_STS_GPE1_STS)
 116         {
 117                 /* XXX -- trawl through GPE1_STS to see what happened */
 118                 output("XXX Unhandled: GPE1_STS (expect lockup)");
 119         }
 120
 121         if (sts & ICH2_SMI_STS_MCSMI_STS)
 122         {
 123                 output("Unhandled: MCSMI_STS");
 124                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
 125         }
 126
 127         if (sts & ICH2_SMI_STS_DEVMON_STS)
 128         {
 129                 unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 130                 unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 131                 unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 132
 133                 if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
 134                 {
 135                         if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
 136                                 output("Unhandled: DEVACT_KBC_ACT_STS");
 137                         else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
 138                                 _handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
 139                         outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
 140                 }
 141
 142                 /* Refresh register cache so that we can print unhandleds as needed. */
 143                 mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 144                 devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 145                 devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 146
 147                 if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
 148                         outputf("Unhandled: MON_SMI (%04x)", mon_smi);
 149                 if (devact_sts & devtrap_en)
 150                         outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
 151         }
 152
 153         if (sts & ICH2_SMI_STS_TCO_STS)
 154         {
 155                 output("Unhandled: TCO_STS");
 156                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
 157         }
 158
 159         if (sts & ICH2_SMI_STS_PERIODIC_STS)
 160         {
 161                 output("Unhandled: PERIODIC_STS");
 162                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
 163         }
 164
 165         if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
 166         {
 167                 output("Unhandled: SERIRQ_SMI_STS");
 168                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
 169         }
 170
 171         if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
 172         {
 173                 output("Unhandled: SMBUS_SMI_STS");
 174                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
 175         }
 176
 177         if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)   /* Either the chipset is buggy, or we are. */
 178                 outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
 179
 180         outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 181                 inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 182                         ICH2_SMI_EN_EOS |
 183                         ICH2_SMI_EN_GBL_SMI_EN);
 184 }
 185
 186 int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
 187 {
 188         if (ev >= SMI_EVENT_MAX)
 189                 return -1;
 190         _handlers[ev] = hnd;
 191         return 0;
 192 }
 193
 194 int smi_enable_event(smi_event_t ev)
 195 {
 196         switch(ev)
 197         {
 198         case SMI_EVENT_FAST_TIMER:
 199                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 200                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 201                                 ICH2_SMI_EN_SWSMI_TMR_EN);
 202                 return 0;
 203         case SMI_EVENT_DEVTRAP_KBC:
 204                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 205                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
 206                                 ICH2_DEVTRAP_EN_KBC_TRP_EN);
 207                 return 0;
 208         default:
 209                 return -1;
 210         }
 211 }
 212
 213 int smi_disable_event(smi_event_t ev)
 214 {
 215         switch(ev)
 216         {
 217         case SMI_EVENT_FAST_TIMER:
 218                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 219                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 220                                 ~ICH2_SMI_EN_SWSMI_TMR_EN);
 221                 return 0;
 222         case SMI_EVENT_DEVTRAP_KBC:
 223                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 224                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
 225                                 ~ICH2_DEVTRAP_EN_KBC_TRP_EN);
 226                 return 0;
 227         default:
 228                 return -1;
 229         }
 230 }