From fb8d158b6c717854cc1697eea6f9013fb401c805 Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Tue, 18 Mar 2008 17:29:26 -0400 Subject: [PATCH 1/1] 76.025MHz, ship it --- Main.v | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/Main.v b/Main.v index 40eac0b..b034663 100644 --- a/Main.v +++ b/Main.v @@ -64,22 +64,23 @@ module NaiveMultiplier( input xsign, ysign, output reg [12:0] out, output reg sign, - output reg [1:0] ovf); + output reg ovf); always @(posedge clk) begin {ovf,out} <= (((y[12] ? (x ) : 0) + (y[11] ? (x >> 1) : 0) + - (y[10] ? (x >> 2) : 0) + - (y[9] ? (x >> 3) : 0)) + - ((y[8] ? (x >> 4) : 0) + - (y[7] ? (x >> 5) : 0) + - (y[6] ? (x >> 6) : 0)))+ + (y[10] ? (x >> 2) : 0)) + + (((y[9] ? (x >> 3) : 0) + + (y[8] ? (x >> 4) : 0))+ + ((y[7] ? (x >> 5) : 0) + + (y[6] ? (x >> 6) : 0))))+ + (((y[5] ? (x >> 7) : 0) + - (y[4] ? (x >> 8) : 0) + + (y[4] ? (x >> 8) : 0)+ (y[3] ? (x >> 9) : 0)) + - ((y[2] ? (x >> 10): 0) + + ((y[2] ? (x >> 10): 0) + (y[1] ? (x >> 11): 0) + (y[0] ? (x >> 12): 0))); sign <= xsign ^ ysign; @@ -93,12 +94,13 @@ module Multiplier( input xsign, ysign, output wire [12:0] out, output wire sign, - output wire [1:0] overflow); + output wire overflow); NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow); endmodule +// Yuq. module MandelUnit( input clk, input [12:0] x, y, @@ -264,8 +266,8 @@ module Mandelbrot( reg [7:0] out; // We detect when the state should be poked by a high negedge followed - // by a high posedge -- if tha thappens, then we're guaranteed that the - // state following the current state will be 100. + // by a high posedge -- if that happens, then we're guaranteed that the + // state following the current state will be 3'b100. reg lastneg; always @(negedge mclk) lastneg <= pixclk; -- 2.43.0