From 772b24130eddc406758d19b13ef30686a82030cc Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 18 Jun 2008 23:29:20 -0400
Subject: [PATCH] Add support for Verilator
---
Main.v | 62 +++++++++++++++++++++-------------------------------------
1 file changed, 22 insertions(+), 40 deletions(-)
diff --git a/Main.v b/Main.v
index 0c1e6dc..165a095 100644
--- a/Main.v
+++ b/Main.v
@@ -5,6 +5,8 @@
* An implementation of a pipelined algorithm to calculate the Mandelbrot set
* in real time on an FPGA.
*/
+
+/* verilator lint_off WIDTH */
`define XRES 640
`define YRES 480
@@ -132,37 +134,7 @@ module MandelUnit(
Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
assign bigsum = r2[13:0] + i2[13:0];
- wire shnasto = bigsum[14];
- wire shnasto2 = // o shi
- ((r[13] & i[13]) |
- ((r[13] ^ i[13]) &
- ((r[12] & i[12]) |
- ((r[12] ^ i[12]) &
- ((r[11] & i[11]) |
- ((r[11] ^ i[11]) &
- ((r[10] & i[10]) |
- ((r[10] ^ i[10]) &
- ((r[ 9] & i[ 9]) |
- ((r[ 9] ^ i[ 9]) &
- ((r[ 8] & i[ 8]) |
- ((r[ 8] ^ i[ 8]) &
- ((r[ 7] & i[ 7]) |
- ((r[ 7] ^ i[ 7]) &
- ((r[ 6] & i[ 6]) |
- ((r[ 6] ^ i[ 6]) &
- ((r[ 5] & i[ 5]) |
- ((r[ 5] ^ i[ 5]) &
- ((r[ 4] & i[ 4]) |
- ((r[ 4] ^ i[ 4]) &
- ((r[ 3] & i[ 3]) |
- ((r[ 3] ^ i[ 3]) &
- ((r[ 2] & i[ 2]) |
- ((r[ 2] ^ i[ 2]) &
- ((r[ 1] & i[ 1]) |
- ((r[ 1] ^ i[ 1]) &
- (r[ 0] & i[ 0])
- ))))))))))))))))))))))))));
- assign bigsum_ovf = shnasto;
+ assign bigsum_ovf = bigsum[14];
assign twocdiff = r2 - i2;
assign diff = twocdiff[15] ? -twocdiff : twocdiff;
@@ -239,8 +211,8 @@ module Mandelbrot(
wire [13:0] nx, ny;
wire rxsign, rysign;
- assign nx = x + xofs;
- assign ny = y + yofs;
+ assign nx = {2'b0,x} + {2'b0,xofs};
+ assign ny = {2'b0,y} + {2'b0,yofs};
assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
assign rxsign = nx[13];
assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
@@ -253,12 +225,14 @@ module Mandelbrot(
wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
wire [7:0] curiter[`MAXOUTN:0];
- reg [14:0] initx, inity, initr, initi;
+ reg [12:0] initx, inity;
+ reg [14:0] initr, initi;
reg [7:0] initci, initb;
reg initxs, initys, initrs, initis;
// Values after the number of iterations denoted by the subscript.
- reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
+ reg [12:0] stagex [2:1], stagey [2:1];
+ reg [14:0] stager [2:1], stagei [2:1];
reg [7:0] stageci [2:1], stageb [2:1];
reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
@@ -274,10 +248,10 @@ module Mandelbrot(
inity <= (state[2]) ? ry :
(state[0]) ? stagey[1] :
(state[1]) ? stagey[2] : 0;
- initr <= (state[2]) ? rx :
+ initr <= (state[2]) ? {2'b0,rx} :
(state[0]) ? stager[1] :
(state[1]) ? stager[2] : 0;
- initi <= (state[2]) ? ry :
+ initi <= (state[2]) ? {2'b0,ry} :
(state[0]) ? stagei[1] :
(state[1]) ? stagei[2] : 0;
initxs <= (state[2]) ? rxsign :
@@ -318,6 +292,7 @@ module Mandelbrot(
3'b001: state <= 3'b010;
3'b010: state <= 3'b100;
3'b100: state <= 3'b001;
+ default: begin $display("invalid state"); $finish; end
endcase
// Data output handling
@@ -402,12 +377,18 @@ module Logo(
endmodule
module MandelTop(
+`ifdef verilator
+ input pixclk, mclk,
+`else
input gclk, output wire dcmok,
+`endif
output wire vs, hs,
output wire [2:0] red, green, output [1:0] blue,
input left, right, up, down, rst, cycle, logooff,
input [2:0] scale);
-
+
+`ifdef verilator
+`else
wire pixclk, mclk, clk;
wire dcm1ok, dcm2ok;
assign dcmok = dcm1ok && dcm2ok;
@@ -425,7 +406,8 @@ module MandelTop(
.CLKFX_OUT(mclk),
.LOCKED_OUT(dcm2ok)
);
-
+`endif
+
wire border;
wire [11:0] x, y;
reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
@@ -438,7 +420,7 @@ module MandelTop(
wire [1:0] mandelb, logob;
SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
- Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
+ Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 8'b0, scale, mandelr, mandelg, mandelb);
Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
assign {red,green,blue} =
--
2.43.0