From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 19 Mar 2008 06:29:07 +0000 (-0400)
Subject: Drop a bit from the overflow.  Rewrite the assigns.
X-Git-Tag: PRE_ROLLBACK~7
X-Git-Url: http://git.joshuawise.com/mandelfpga.git/commitdiff_plain/a3a4354bafd8467e9b79c037314da6644f41b470?ds=inline;hp=fb8d158b6c717854cc1697eea6f9013fb401c805

Drop a bit from the overflow.  Rewrite the assigns.
---

diff --git a/Main.v b/Main.v
index b034663..aacfdab 100644
--- a/Main.v
+++ b/Main.v
@@ -117,7 +117,7 @@ module MandelUnit(
 	wire [14:0] r2, i2, ri, diff;
 	wire [15:0] twocdiff;
 	wire r2sign, i2sign, risign, dsign;
-	wire [16:0] bigsum;
+	wire [15:0] bigsum;
 	wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
 
 	reg [12:0] xd, yd;
@@ -127,12 +127,12 @@ module MandelUnit(
 
 	assign ri[0] = 0;
 
-	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
-	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
-	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
+	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
+	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
+	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
 
 	assign bigsum = r2 + i2;
-	assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
+	assign bigsum_ovf = bigsum[15] | bigsum[14];
 	assign rin_ovf = rd;
 	assign iin_ovf = id;
 	assign twocdiff = r2 - i2;
@@ -212,7 +212,6 @@ module Mandelbrot(
 	assign rxsign = nx[13];
 	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
 	assign rysign = ny[13];
-	
 
 	wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
 	wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
@@ -232,36 +231,36 @@ module Mandelbrot(
 	
 	reg [2:0] state = 3'b001;	// One-hot encoded state.
 	
-	assign initx = state[0] ? rx :
-	               state[1] ? stagex[1] :
-	               stagex[2];
-	assign inity = state[0] ? ry :
-	               state[1] ? stagey[1] :
-	               stagey[2];
-	assign initr = state[0] ? rx :
-	               state[1] ? stager[1] :
-	               stager[2];
-	assign initi = state[0] ? ry :
-	               state[1] ? stagei[1] :
-	               stagei[2];
-	assign initxs = state[0] ? rxsign :
-	                state[1] ? stagexs[1] :
-	                stagexs[2];
-	assign initys = state[0] ? rysign :
-	                state[1] ? stageys[1] :
-	                stageys[2];
-	assign initrs = state[0] ? rxsign :
-	                state[1] ? stagers[1] :
-	                stagers[2];
-	assign initis = state[0] ? rysign :
-	                state[1] ? stageis[1] :
-	                stageis[2];
-	assign initb = state[0] ? 8'b11111111 :
-	               state[1] ? stageb[1] :
-	               stageb[2];
-	assign initci = state[0] ? 8'b00000000 :
-	                state[1] ? stageci[1] : 
-	                stageci[2];
+	assign initx = (state[0]) ? rx :
+	               (state[1]) ? stagex[1] :
+	               (state[2]) ? stagex[2] : 0;
+	assign inity = (state[0]) ? ry :
+	               (state[1]) ? stagey[1] :
+	               (state[2]) ? stagey[2] : 0;
+	assign initr = (state[0]) ? rx :
+	               (state[1]) ? stager[1] :
+	               (state[2]) ? stager[2] : 0;
+	assign initi = (state[0]) ? ry :
+	               (state[1]) ? stagei[1] :
+	               (state[2]) ? stagei[2] : 0;
+	assign initxs = (state[0]) ? rxsign :
+	                (state[1]) ? stagexs[1] :
+	                (state[2]) ? stagexs[2] : 0;
+	assign initys = (state[0]) ? rysign :
+	                (state[1]) ? stageys[1] :
+	                (state[2]) ? stageys[2] : 0;
+	assign initrs = (state[0]) ? rxsign :
+	                (state[1]) ? stagers[1] :
+	                (state[2]) ? stagers[2] : 0;
+	assign initis = (state[0]) ? rysign :
+	                (state[1]) ? stageis[1] :
+	                (state[2]) ? stageis[2] : 0;
+	assign initb = (state[0]) ? 8'b11111111 :
+	               (state[1]) ? stageb[1] :
+	               (state[2]) ? stageb[2] : 0;
+	assign initci = (state[0]) ? 8'b00000000 :
+	                (state[1]) ? stageci[1] : 
+	                (state[2]) ? stageci[2] : 0;
 	
 	reg [7:0] out;
 	
@@ -277,7 +276,11 @@ module Mandelbrot(
 		if (lastneg && pixclk)	// If a pixclk has happened, the state should be reset.
 			state <= 3'b100;
 		else						// Otherwise, just poke it forward.
-			state <= {state[1], state[0], state[2]};
+			case(state)
+			3'b001: state <= 3'b010;
+			3'b010: state <= 3'b100;
+			3'b100: state <= 3'b001;
+			endcase
 	
 		// Data output handling
 		if (state[0]) begin