From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 16 Mar 2008 00:22:23 +0000 (-0400)
Subject: Working 13 bit.
X-Git-Tag: PRE_ROLLBACK~18
X-Git-Url: http://git.joshuawise.com/mandelfpga.git/commitdiff_plain/92e851e150660529b5d871132c11a3e0c0101406?ds=inline;hp=05c0805be5682a94d874a89f05f01d1830941a70

Working 13 bit.
---

diff --git a/Main.v b/Main.v
index 2dd4764..9e976d8 100644
--- a/Main.v
+++ b/Main.v
@@ -89,9 +89,9 @@ endmodule
 
 module Multiplier(
 	input clk,
-	input [11:0] x, y,
+	input [12:0] x, y,
 	input xsign, ysign,
-	output wire [11:0] out,
+	output wire [12:0] out,
 	output wire sign,
 	output wire [1:0] overflow);
 
@@ -103,16 +103,16 @@ module MandelUnit(
 	input clk,
 	input [12:0] x, y,
 	input xsign, ysign,
-	input [13:0] r, i,
+	input [14:0] r, i,
 	input rsign, isign,
 	input [7:0] ibail, icuriter,
 	output reg [12:0] xout, yout,
 	output reg xsout, ysout,
-	output reg [13:0] rout, iout,
+	output reg [14:0] rout, iout,
 	output reg rsout, isout,
 	output reg [7:0] obail, ocuriter);
 
-	wire [13:0] r2, i2, ri, diff;
+	wire [14:0] r2, i2, ri, diff;
 	wire r2sign, i2sign, risign, dsign;
 	wire [16:0] bigsum;
 	wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
@@ -124,9 +124,9 @@ module MandelUnit(
 
 	assign ri[0] = 0;
 
-	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
-	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
-	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, throwaway);
+	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
+	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
+	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
 
 	assign bigsum = r2 + i2;
 	assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
@@ -147,8 +147,8 @@ module MandelUnit(
 		ysout <= ysd;
 		ibaild <= ibail;
 		curiterd <= icuriter;
-		rd <= r[13];
-		id <= i[13];
+		rd <= r[13] | r[14];
+		id <= i[13] | i[14];
 
 		if (xsd ^ dsign) begin
 			if (diff > xd) begin
@@ -191,7 +191,7 @@ module Mandelbrot(
 	input mclk,
 	input pixclk,
 	input [11:0] x, y,
-	input [12:0] xofs, yofs,
+	input [13:0] xofs, yofs,
 	input [7:0] colorofs,
 	input [2:0] scale,
 	output reg [2:0] red, green, output reg [1:0] blue);
@@ -208,7 +208,7 @@ module Mandelbrot(
 	assign rysign = ny[13];
 	
 
-	wire [13:0] mr[9:0], mi[9:0];
+	wire [14:0] mr[9:0], mi[9:0];
 	wire mrs[9:0], mis[9:0];
 	wire [7:0] mb[9:0];
 	wire [12:0] xprop[9:0], yprop[9:0];
@@ -219,7 +219,7 @@ module Mandelbrot(
 	wire [7:0] initci, initb;
 	wire initxs, initys, initrs, initis;
 	
-	reg [13:0] loopx, loopy, loopr, loopi;
+	reg [14:0] loopx, loopy, loopr, loopi;
 	reg [7:0] loopci, loopb;
 	reg loopxs, loopys, looprs, loopis;
 	
@@ -336,7 +336,7 @@ module MandelTop(
 	wire [7:0] zero = 8'b0;
 	wire clk;
 	wire [11:0] x, y;
-	reg [12:0] xofs = -`XRES/2, yofs = -`YRES/2;
+	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
 	reg [5:0] slowctr = 0;
 	reg [7:0] colorcycle = 0;
 	wire [11:0] realx, realy;