From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 19 Mar 2008 07:01:45 +0000 (-0400)
Subject: Reg the init variables -- takes us to 83.842MHz! 8678 LUTs, 4694 slices post synthesis.
X-Git-Tag: PRE_ROLLBACK~6
X-Git-Url: http://git.joshuawise.com/mandelfpga.git/commitdiff_plain/79af494a1f40aff429c60355790bf6bb0c81c51e?ds=sidebyside

Reg the init variables -- takes us to 83.842MHz! 8678 LUTs, 4694 slices post synthesis.
---

diff --git a/Main.v b/Main.v
index aacfdab..2ae7962 100644
--- a/Main.v
+++ b/Main.v
@@ -220,9 +220,9 @@ module Mandelbrot(
 	wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
 	wire [7:0] curiter[`MAXOUTN:0];
 	
-	wire [14:0] initx, inity, initr, initi;
-	wire [7:0] initci, initb;
-	wire initxs, initys, initrs, initis;
+	reg [14:0] initx, inity, initr, initi;
+	reg [7:0] initci, initb;
+	reg initxs, initys, initrs, initis;
 	
 	// Values after the number of iterations denoted by the subscript.
 	reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
@@ -231,36 +231,41 @@ module Mandelbrot(
 	
 	reg [2:0] state = 3'b001;	// One-hot encoded state.
 	
-	assign initx = (state[0]) ? rx :
-	               (state[1]) ? stagex[1] :
-	               (state[2]) ? stagex[2] : 0;
-	assign inity = (state[0]) ? ry :
-	               (state[1]) ? stagey[1] :
-	               (state[2]) ? stagey[2] : 0;
-	assign initr = (state[0]) ? rx :
-	               (state[1]) ? stager[1] :
-	               (state[2]) ? stager[2] : 0;
-	assign initi = (state[0]) ? ry :
-	               (state[1]) ? stagei[1] :
-	               (state[2]) ? stagei[2] : 0;
-	assign initxs = (state[0]) ? rxsign :
-	                (state[1]) ? stagexs[1] :
-	                (state[2]) ? stagexs[2] : 0;
-	assign initys = (state[0]) ? rysign :
-	                (state[1]) ? stageys[1] :
-	                (state[2]) ? stageys[2] : 0;
-	assign initrs = (state[0]) ? rxsign :
-	                (state[1]) ? stagers[1] :
-	                (state[2]) ? stagers[2] : 0;
-	assign initis = (state[0]) ? rysign :
-	                (state[1]) ? stageis[1] :
-	                (state[2]) ? stageis[2] : 0;
-	assign initb = (state[0]) ? 8'b11111111 :
-	               (state[1]) ? stageb[1] :
-	               (state[2]) ? stageb[2] : 0;
-	assign initci = (state[0]) ? 8'b00000000 :
-	                (state[1]) ? stageci[1] : 
-	                (state[2]) ? stageci[2] : 0;
+	// States are advanced one from what they should be, so that they'll
+	// get there on the _next_ mclk.
+	always @(posedge mclk)
+	begin
+		initx <= (state[2]) ? rx :
+	            (state[0]) ? stagex[1] :
+	            (state[1]) ? stagex[2] : 0;
+		inity <= (state[2]) ? ry :
+	               (state[0]) ? stagey[1] :
+	               (state[1]) ? stagey[2] : 0;
+		initr <= (state[2]) ? rx :
+	               (state[0]) ? stager[1] :
+	               (state[1]) ? stager[2] : 0;
+		initi <= (state[2]) ? ry :
+	               (state[0]) ? stagei[1] :
+	               (state[1]) ? stagei[2] : 0;
+		initxs <= (state[2]) ? rxsign :
+	                (state[0]) ? stagexs[1] :
+	                (state[1]) ? stagexs[2] : 0;
+		initys <= (state[2]) ? rysign :
+	                (state[0]) ? stageys[1] :
+	                (state[1]) ? stageys[2] : 0;
+		initrs <= (state[2]) ? rxsign :
+	                (state[0]) ? stagers[1] :
+	                (state[1]) ? stagers[2] : 0;
+		initis <= (state[2]) ? rysign :
+	                (state[0]) ? stageis[1] :
+	                (state[1]) ? stageis[2] : 0;
+		initb <= (state[2]) ? 8'b11111111 :
+	               (state[0]) ? stageb[1] :
+	               (state[1]) ? stageb[2] : 0;
+		initci <= (state[2]) ? 8'b00000000 :
+	                (state[0]) ? stageci[1] : 
+	                (state[1]) ? stageci[2] : 0;
+	end
 	
 	reg [7:0] out;