From: Joshua Wise Date: Thu, 20 Mar 2008 18:19:46 +0000 (-0400) Subject: Clean up and turn the iout and rout into twos comp. I think this made our slice... X-Git-Tag: PRE_ROLLBACK~5 X-Git-Url: http://git.joshuawise.com/mandelfpga.git/commitdiff_plain/2afeab21dbcfb1b0e2bcfadc146d061347d2c94e?hp=79af494a1f40aff429c60355790bf6bb0c81c51e Clean up and turn the iout and rout into twos comp. I think this made our slice count a little worse, but oh well. 4709 postsynth --- diff --git a/Main.v b/Main.v index 2ae7962..ccc11c7 100644 --- a/Main.v +++ b/Main.v @@ -121,7 +121,7 @@ module MandelUnit( wire bigsum_ovf, rin_ovf, iin_ovf, throwaway; reg [12:0] xd, yd; - reg rd, id; + reg ineedbaild; reg xsd, ysd; reg [7:0] ibaild, curiterd; @@ -133,11 +133,13 @@ module MandelUnit( assign bigsum = r2 + i2; assign bigsum_ovf = bigsum[15] | bigsum[14]; - assign rin_ovf = rd; - assign iin_ovf = id; + assign twocdiff = r2 - i2; assign diff = twocdiff[15] ? -twocdiff : twocdiff; assign dsign = twocdiff[15]; + + wire [15:0] twocrout = xd - diff; + wire [15:0] twociout = yd - ri; always @ (posedge clk) begin @@ -151,28 +153,29 @@ module MandelUnit( ysout <= ysd; ibaild <= ibail; curiterd <= icuriter; - rd <= r[13] | r[14]; - id <= i[13] | i[14]; + ineedbaild <= r[13] | r[14] | i[13] | i[14]; + // r^2 - i^2 + x if (xsd ^ dsign) begin - if (diff > xd) begin - rout <= diff - xd; + if (twocrout[15]) begin // diff > xd + rout <= -twocrout; rsout <= dsign; end else begin - rout <= xd - diff; + rout <= twocrout; rsout <= xsd; end end else begin rout <= diff + xd; - rsout <= xsd; + rsout <= xsd; // xsd == dsign end + // 2 * r * i + y if (ysd ^ risign) begin - if (ri > yd) begin - iout <= ri - yd; + if (twociout[15]) begin // ri > yd + iout <= -twociout; isout <= risign; end else begin - iout <= yd - ri; + iout <= twociout; isout <= ysd; end end else begin @@ -182,7 +185,7 @@ module MandelUnit( // If we haven't bailed out, and we meet any of the bailout conditions, // bail out now. Otherwise, leave the bailout at whatever it was before. - if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf)) + if ((ibaild == 255) && (bigsum_ovf | ineedbaild)) obail <= curiterd; else obail <= ibaild; @@ -423,8 +426,6 @@ module MandelTop( wire [2:0] mandelr, mandelg, logor, logog; wire [1:0] mandelb, logob; - - SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border); Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb); Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);