X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/a3a4354bafd8467e9b79c037314da6644f41b470..2afeab21dbcfb1b0e2bcfadc146d061347d2c94e:/Main.v?ds=sidebyside

diff --git a/Main.v b/Main.v
index aacfdab..ccc11c7 100644
--- a/Main.v
+++ b/Main.v
@@ -121,7 +121,7 @@ module MandelUnit(
 	wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
 
 	reg [12:0] xd, yd;
-	reg rd, id;
+	reg ineedbaild;
 	reg xsd, ysd;
 	reg [7:0] ibaild, curiterd;
 
@@ -133,11 +133,13 @@ module MandelUnit(
 
 	assign bigsum = r2 + i2;
 	assign bigsum_ovf = bigsum[15] | bigsum[14];
-	assign rin_ovf = rd;
-	assign iin_ovf = id;
+	
 	assign twocdiff = r2 - i2;
 	assign diff = twocdiff[15] ? -twocdiff : twocdiff;
 	assign dsign = twocdiff[15];
+	
+	wire [15:0] twocrout = xd - diff;
+	wire [15:0] twociout = yd - ri;
 
 	always @ (posedge clk)
 	begin
@@ -151,28 +153,29 @@ module MandelUnit(
 		ysout <= ysd;
 		ibaild <= ibail;
 		curiterd <= icuriter;
-		rd <= r[13] | r[14];
-		id <= i[13] | i[14];
+		ineedbaild <= r[13] | r[14] | i[13] | i[14];
 
+		// r^2 - i^2 + x
 		if (xsd ^ dsign) begin
-			if (diff > xd) begin
-				rout <= diff - xd;
+			if (twocrout[15]) begin	// diff > xd
+				rout <= -twocrout;
 				rsout <= dsign;
 			end else begin
-				rout <= xd - diff;
+				rout <= twocrout;
 				rsout <= xsd;
 			end
 		end else begin
 			rout <= diff + xd;
-			rsout <= xsd;
+			rsout <= xsd;	// xsd == dsign
 		end
 		
+		// 2 * r * i + y
 		if (ysd ^ risign) begin
-			if (ri > yd) begin
-				iout <= ri - yd;
+			if (twociout[15]) begin	// ri > yd
+				iout <= -twociout;
 				isout <= risign;
 			end else begin
-				iout <= yd - ri;
+				iout <= twociout;
 				isout <= ysd;
 			end
 		end else begin
@@ -182,7 +185,7 @@ module MandelUnit(
 		
 		// If we haven't bailed out, and we meet any of the bailout conditions,
 		// bail out now.  Otherwise, leave the bailout at whatever it was before.
-		if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
+		if ((ibaild == 255) && (bigsum_ovf | ineedbaild))
 			obail <= curiterd;
 		else
 			obail <= ibaild;
@@ -220,9 +223,9 @@ module Mandelbrot(
 	wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
 	wire [7:0] curiter[`MAXOUTN:0];
 	
-	wire [14:0] initx, inity, initr, initi;
-	wire [7:0] initci, initb;
-	wire initxs, initys, initrs, initis;
+	reg [14:0] initx, inity, initr, initi;
+	reg [7:0] initci, initb;
+	reg initxs, initys, initrs, initis;
 	
 	// Values after the number of iterations denoted by the subscript.
 	reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
@@ -231,36 +234,41 @@ module Mandelbrot(
 	
 	reg [2:0] state = 3'b001;	// One-hot encoded state.
 	
-	assign initx = (state[0]) ? rx :
-	               (state[1]) ? stagex[1] :
-	               (state[2]) ? stagex[2] : 0;
-	assign inity = (state[0]) ? ry :
-	               (state[1]) ? stagey[1] :
-	               (state[2]) ? stagey[2] : 0;
-	assign initr = (state[0]) ? rx :
-	               (state[1]) ? stager[1] :
-	               (state[2]) ? stager[2] : 0;
-	assign initi = (state[0]) ? ry :
-	               (state[1]) ? stagei[1] :
-	               (state[2]) ? stagei[2] : 0;
-	assign initxs = (state[0]) ? rxsign :
-	                (state[1]) ? stagexs[1] :
-	                (state[2]) ? stagexs[2] : 0;
-	assign initys = (state[0]) ? rysign :
-	                (state[1]) ? stageys[1] :
-	                (state[2]) ? stageys[2] : 0;
-	assign initrs = (state[0]) ? rxsign :
-	                (state[1]) ? stagers[1] :
-	                (state[2]) ? stagers[2] : 0;
-	assign initis = (state[0]) ? rysign :
-	                (state[1]) ? stageis[1] :
-	                (state[2]) ? stageis[2] : 0;
-	assign initb = (state[0]) ? 8'b11111111 :
-	               (state[1]) ? stageb[1] :
-	               (state[2]) ? stageb[2] : 0;
-	assign initci = (state[0]) ? 8'b00000000 :
-	                (state[1]) ? stageci[1] : 
-	                (state[2]) ? stageci[2] : 0;
+	// States are advanced one from what they should be, so that they'll
+	// get there on the _next_ mclk.
+	always @(posedge mclk)
+	begin
+		initx <= (state[2]) ? rx :
+	            (state[0]) ? stagex[1] :
+	            (state[1]) ? stagex[2] : 0;
+		inity <= (state[2]) ? ry :
+	               (state[0]) ? stagey[1] :
+	               (state[1]) ? stagey[2] : 0;
+		initr <= (state[2]) ? rx :
+	               (state[0]) ? stager[1] :
+	               (state[1]) ? stager[2] : 0;
+		initi <= (state[2]) ? ry :
+	               (state[0]) ? stagei[1] :
+	               (state[1]) ? stagei[2] : 0;
+		initxs <= (state[2]) ? rxsign :
+	                (state[0]) ? stagexs[1] :
+	                (state[1]) ? stagexs[2] : 0;
+		initys <= (state[2]) ? rysign :
+	                (state[0]) ? stageys[1] :
+	                (state[1]) ? stageys[2] : 0;
+		initrs <= (state[2]) ? rxsign :
+	                (state[0]) ? stagers[1] :
+	                (state[1]) ? stagers[2] : 0;
+		initis <= (state[2]) ? rysign :
+	                (state[0]) ? stageis[1] :
+	                (state[1]) ? stageis[2] : 0;
+		initb <= (state[2]) ? 8'b11111111 :
+	               (state[0]) ? stageb[1] :
+	               (state[1]) ? stageb[2] : 0;
+		initci <= (state[2]) ? 8'b00000000 :
+	                (state[0]) ? stageci[1] : 
+	                (state[1]) ? stageci[2] : 0;
+	end
 	
 	reg [7:0] out;
 	
@@ -418,8 +426,6 @@ module MandelTop(
 	wire [2:0] mandelr, mandelg, logor, logog;
 	wire [1:0] mandelb, logob;
 	
-	
-
 	SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
 	Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
 	Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);