X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/9032b2b5f7475dc07709aa2e51f9a014f76760c0..c3ed4329c4a2afcf90da4d9d26aae5b5af97c1e6:/Main.v?ds=inline diff --git a/Main.v b/Main.v index 42e614a..40eac0b 100644 --- a/Main.v +++ b/Main.v @@ -198,7 +198,7 @@ module Mandelbrot( input [2:0] scale, output reg [2:0] red, green, output reg [1:0] blue); -`define MAXOUTN 12 +`define MAXOUTN 11 wire [12:0] rx, ry; wire [13:0] nx, ny; @@ -223,51 +223,93 @@ module Mandelbrot( wire [7:0] initci, initb; wire initxs, initys, initrs, initis; - reg [14:0] loopx, loopy, loopr, loopi; - reg [7:0] loopci, loopb; - reg loopxs, loopys, looprs, loopis; + // Values after the number of iterations denoted by the subscript. + reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1]; + reg [7:0] stageci [2:1], stageb [2:1]; + reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1]; - reg state = 0; + reg [2:0] state = 3'b001; // One-hot encoded state. - // On pixclk = 1, - // A new value to be loaded comes in, and a value in need of loopback comes out. - // On pixclk = 0, - // A new value in need of loopback comes in, and a completed value comes out. - - assign initx = state ? rx : loopx; - assign inity = state ? ry : loopy; - assign initr = state ? rx : loopr; - assign initi = state ? ry : loopi; - assign initxs = state ? rxsign : loopxs; - assign initys = state ? rysign : loopys; - assign initrs = state ? rxsign : looprs; - assign initis = state ? rysign : loopis; - assign initb = state ? 8'b11111111 : loopb; - assign initci = state ? 8'b00000000 : loopci; + assign initx = state[0] ? rx : + state[1] ? stagex[1] : + stagex[2]; + assign inity = state[0] ? ry : + state[1] ? stagey[1] : + stagey[2]; + assign initr = state[0] ? rx : + state[1] ? stager[1] : + stager[2]; + assign initi = state[0] ? ry : + state[1] ? stagei[1] : + stagei[2]; + assign initxs = state[0] ? rxsign : + state[1] ? stagexs[1] : + stagexs[2]; + assign initys = state[0] ? rysign : + state[1] ? stageys[1] : + stageys[2]; + assign initrs = state[0] ? rxsign : + state[1] ? stagers[1] : + stagers[2]; + assign initis = state[0] ? rysign : + state[1] ? stageis[1] : + stageis[2]; + assign initb = state[0] ? 8'b11111111 : + state[1] ? stageb[1] : + stageb[2]; + assign initci = state[0] ? 8'b00000000 : + state[1] ? stageci[1] : + stageci[2]; reg [7:0] out; - reg pixclksync; + + // We detect when the state should be poked by a high negedge followed + // by a high posedge -- if tha thappens, then we're guaranteed that the + // state following the current state will be 100. + reg lastneg; always @(negedge mclk) - pixclksync <= ~pixclk; + lastneg <= pixclk; always @(posedge mclk) begin - if (!state) begin - out <= ~mb[`MAXOUTN] + colorofs; - end else begin + if (lastneg && pixclk) // If a pixclk has happened, the state should be reset. + state <= 3'b100; + else // Otherwise, just poke it forward. + state <= {state[1], state[0], state[2]}; + + // Data output handling + if (state[0]) begin {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]}; - loopx <= xprop[`MAXOUTN]; - loopy <= yprop[`MAXOUTN]; - loopr <= mr[`MAXOUTN]; - loopi <= mi[`MAXOUTN]; - loopxs <= xsprop[`MAXOUTN]; - loopys <= ysprop[`MAXOUTN]; - looprs <= mrs[`MAXOUTN]; - loopis <= mis[`MAXOUTN]; - loopb <= mb[`MAXOUTN]; - loopci <= curiter[`MAXOUTN]; end - state <= ~pixclksync; + if (state[1]) begin + out <= ~mb[`MAXOUTN] + colorofs; + end + + if (state[0]) begin // PnR0 in, PnR2 out + stagex[2] <= xprop[`MAXOUTN]; + stagey[2] <= yprop[`MAXOUTN]; + stager[2] <= mr[`MAXOUTN]; + stagei[2] <= mi[`MAXOUTN]; + stagexs[2] <= xsprop[`MAXOUTN]; + stageys[2] <= ysprop[`MAXOUTN]; + stagers[2] <= mrs[`MAXOUTN]; + stageis[2] <= mis[`MAXOUTN]; + stageb[2] <= mb[`MAXOUTN]; + stageci[2] <= curiter[`MAXOUTN]; + end + + if (state[2]) begin // PnR2 in, PnR1 out + stagex[1] <= xprop[`MAXOUTN]; + stagey[1] <= yprop[`MAXOUTN]; + stager[1] <= mr[`MAXOUTN]; + stagei[1] <= mi[`MAXOUTN]; + stagexs[1] <= xsprop[`MAXOUTN]; + stageys[1] <= ysprop[`MAXOUTN]; + stagers[1] <= mrs[`MAXOUTN]; + stageis[1] <= mis[`MAXOUTN]; + stageb[1] <= mb[`MAXOUTN]; + stageci[1] <= curiter[`MAXOUTN]; + end end MandelUnit mu0( @@ -312,9 +354,6 @@ module Mandelbrot( MandelUnit mub(mclk, xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10], xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]); - MandelUnit muc(mclk, - xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11], - xprop[12], yprop[12], xsprop[12], ysprop[12], mr[12], mi[12], mrs[12], mis[12], mb[12], curiter[12]); endmodule @@ -344,10 +383,26 @@ module MandelTop( input left, right, up, down, rst, cycle, logooff, input [2:0] scale); + + wire pixclk, mclk, gclk2, clk; + wire dcm1ok, dcm2ok; + assign dcmok = dcm1ok && dcm2ok; + + IBUFG typeA(.O(clk), .I(gclk)); + + pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz + .CLKIN_IN(clk), + .CLKFX_OUT(pixclk), + .LOCKED_OUT(dcm1ok) + ); + + mandelDCM dcm2( + .CLKIN_IN(clk), + .CLKFX_OUT(mclk), + .LOCKED_OUT(dcm2ok) + ); + wire border; - wire pixclk; - wire [7:0] zero = 8'b0; - wire clk; wire [11:0] x, y; reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2; reg [5:0] slowctr = 0; @@ -358,15 +413,10 @@ module MandelTop( wire [2:0] mandelr, mandelg, logor, logog; wire [1:0] mandelb, logob; - pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz - .CLKIN_IN(gclk), - .CLKFX_OUT(pixclk), - .CLKIN_IBUFG_OUT(clk), - .LOCKED_OUT(dcmok) - ); + SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border); - Mandelbrot mandel(clk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb); + Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb); Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob); assign {red,green,blue} =