X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/9032b2b5f7475dc07709aa2e51f9a014f76760c0..2afeab21dbcfb1b0e2bcfadc146d061347d2c94e:/Main.v?ds=inline diff --git a/Main.v b/Main.v index 42e614a..ccc11c7 100644 --- a/Main.v +++ b/Main.v @@ -64,22 +64,23 @@ module NaiveMultiplier( input xsign, ysign, output reg [12:0] out, output reg sign, - output reg [1:0] ovf); + output reg ovf); always @(posedge clk) begin {ovf,out} <= (((y[12] ? (x ) : 0) + (y[11] ? (x >> 1) : 0) + - (y[10] ? (x >> 2) : 0) + - (y[9] ? (x >> 3) : 0)) + - ((y[8] ? (x >> 4) : 0) + - (y[7] ? (x >> 5) : 0) + - (y[6] ? (x >> 6) : 0)))+ + (y[10] ? (x >> 2) : 0)) + + (((y[9] ? (x >> 3) : 0) + + (y[8] ? (x >> 4) : 0))+ + ((y[7] ? (x >> 5) : 0) + + (y[6] ? (x >> 6) : 0))))+ + (((y[5] ? (x >> 7) : 0) + - (y[4] ? (x >> 8) : 0) + + (y[4] ? (x >> 8) : 0)+ (y[3] ? (x >> 9) : 0)) + - ((y[2] ? (x >> 10): 0) + + ((y[2] ? (x >> 10): 0) + (y[1] ? (x >> 11): 0) + (y[0] ? (x >> 12): 0))); sign <= xsign ^ ysign; @@ -93,12 +94,13 @@ module Multiplier( input xsign, ysign, output wire [12:0] out, output wire sign, - output wire [1:0] overflow); + output wire overflow); NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow); endmodule +// Yuq. module MandelUnit( input clk, input [12:0] x, y, @@ -115,27 +117,29 @@ module MandelUnit( wire [14:0] r2, i2, ri, diff; wire [15:0] twocdiff; wire r2sign, i2sign, risign, dsign; - wire [16:0] bigsum; + wire [15:0] bigsum; wire bigsum_ovf, rin_ovf, iin_ovf, throwaway; reg [12:0] xd, yd; - reg rd, id; + reg ineedbaild; reg xsd, ysd; reg [7:0] ibaild, curiterd; assign ri[0] = 0; - Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]); - Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]); - Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]}); + Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]); + Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]); + Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]); assign bigsum = r2 + i2; - assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14]; - assign rin_ovf = rd; - assign iin_ovf = id; + assign bigsum_ovf = bigsum[15] | bigsum[14]; + assign twocdiff = r2 - i2; assign diff = twocdiff[15] ? -twocdiff : twocdiff; assign dsign = twocdiff[15]; + + wire [15:0] twocrout = xd - diff; + wire [15:0] twociout = yd - ri; always @ (posedge clk) begin @@ -149,28 +153,29 @@ module MandelUnit( ysout <= ysd; ibaild <= ibail; curiterd <= icuriter; - rd <= r[13] | r[14]; - id <= i[13] | i[14]; + ineedbaild <= r[13] | r[14] | i[13] | i[14]; + // r^2 - i^2 + x if (xsd ^ dsign) begin - if (diff > xd) begin - rout <= diff - xd; + if (twocrout[15]) begin // diff > xd + rout <= -twocrout; rsout <= dsign; end else begin - rout <= xd - diff; + rout <= twocrout; rsout <= xsd; end end else begin rout <= diff + xd; - rsout <= xsd; + rsout <= xsd; // xsd == dsign end + // 2 * r * i + y if (ysd ^ risign) begin - if (ri > yd) begin - iout <= ri - yd; + if (twociout[15]) begin // ri > yd + iout <= -twociout; isout <= risign; end else begin - iout <= yd - ri; + iout <= twociout; isout <= ysd; end end else begin @@ -180,7 +185,7 @@ module MandelUnit( // If we haven't bailed out, and we meet any of the bailout conditions, // bail out now. Otherwise, leave the bailout at whatever it was before. - if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf)) + if ((ibaild == 255) && (bigsum_ovf | ineedbaild)) obail <= curiterd; else obail <= ibaild; @@ -198,7 +203,7 @@ module Mandelbrot( input [2:0] scale, output reg [2:0] red, green, output reg [1:0] blue); -`define MAXOUTN 12 +`define MAXOUTN 11 wire [12:0] rx, ry; wire [13:0] nx, ny; @@ -210,7 +215,6 @@ module Mandelbrot( assign rxsign = nx[13]; assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale; assign rysign = ny[13]; - wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0]; wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0]; @@ -219,55 +223,106 @@ module Mandelbrot( wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0]; wire [7:0] curiter[`MAXOUTN:0]; - wire [14:0] initx, inity, initr, initi; - wire [7:0] initci, initb; - wire initxs, initys, initrs, initis; - - reg [14:0] loopx, loopy, loopr, loopi; - reg [7:0] loopci, loopb; - reg loopxs, loopys, looprs, loopis; + reg [14:0] initx, inity, initr, initi; + reg [7:0] initci, initb; + reg initxs, initys, initrs, initis; - reg state = 0; + // Values after the number of iterations denoted by the subscript. + reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1]; + reg [7:0] stageci [2:1], stageb [2:1]; + reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1]; - // On pixclk = 1, - // A new value to be loaded comes in, and a value in need of loopback comes out. - // On pixclk = 0, - // A new value in need of loopback comes in, and a completed value comes out. + reg [2:0] state = 3'b001; // One-hot encoded state. - assign initx = state ? rx : loopx; - assign inity = state ? ry : loopy; - assign initr = state ? rx : loopr; - assign initi = state ? ry : loopi; - assign initxs = state ? rxsign : loopxs; - assign initys = state ? rysign : loopys; - assign initrs = state ? rxsign : looprs; - assign initis = state ? rysign : loopis; - assign initb = state ? 8'b11111111 : loopb; - assign initci = state ? 8'b00000000 : loopci; + // States are advanced one from what they should be, so that they'll + // get there on the _next_ mclk. + always @(posedge mclk) + begin + initx <= (state[2]) ? rx : + (state[0]) ? stagex[1] : + (state[1]) ? stagex[2] : 0; + inity <= (state[2]) ? ry : + (state[0]) ? stagey[1] : + (state[1]) ? stagey[2] : 0; + initr <= (state[2]) ? rx : + (state[0]) ? stager[1] : + (state[1]) ? stager[2] : 0; + initi <= (state[2]) ? ry : + (state[0]) ? stagei[1] : + (state[1]) ? stagei[2] : 0; + initxs <= (state[2]) ? rxsign : + (state[0]) ? stagexs[1] : + (state[1]) ? stagexs[2] : 0; + initys <= (state[2]) ? rysign : + (state[0]) ? stageys[1] : + (state[1]) ? stageys[2] : 0; + initrs <= (state[2]) ? rxsign : + (state[0]) ? stagers[1] : + (state[1]) ? stagers[2] : 0; + initis <= (state[2]) ? rysign : + (state[0]) ? stageis[1] : + (state[1]) ? stageis[2] : 0; + initb <= (state[2]) ? 8'b11111111 : + (state[0]) ? stageb[1] : + (state[1]) ? stageb[2] : 0; + initci <= (state[2]) ? 8'b00000000 : + (state[0]) ? stageci[1] : + (state[1]) ? stageci[2] : 0; + end reg [7:0] out; - reg pixclksync; + + // We detect when the state should be poked by a high negedge followed + // by a high posedge -- if that happens, then we're guaranteed that the + // state following the current state will be 3'b100. + reg lastneg; always @(negedge mclk) - pixclksync <= ~pixclk; + lastneg <= pixclk; always @(posedge mclk) begin - if (!state) begin - out <= ~mb[`MAXOUTN] + colorofs; - end else begin + if (lastneg && pixclk) // If a pixclk has happened, the state should be reset. + state <= 3'b100; + else // Otherwise, just poke it forward. + case(state) + 3'b001: state <= 3'b010; + 3'b010: state <= 3'b100; + 3'b100: state <= 3'b001; + endcase + + // Data output handling + if (state[0]) begin {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]}; - loopx <= xprop[`MAXOUTN]; - loopy <= yprop[`MAXOUTN]; - loopr <= mr[`MAXOUTN]; - loopi <= mi[`MAXOUTN]; - loopxs <= xsprop[`MAXOUTN]; - loopys <= ysprop[`MAXOUTN]; - looprs <= mrs[`MAXOUTN]; - loopis <= mis[`MAXOUTN]; - loopb <= mb[`MAXOUTN]; - loopci <= curiter[`MAXOUTN]; end - state <= ~pixclksync; + if (state[1]) begin + out <= ~mb[`MAXOUTN] + colorofs; + end + + if (state[0]) begin // PnR0 in, PnR2 out + stagex[2] <= xprop[`MAXOUTN]; + stagey[2] <= yprop[`MAXOUTN]; + stager[2] <= mr[`MAXOUTN]; + stagei[2] <= mi[`MAXOUTN]; + stagexs[2] <= xsprop[`MAXOUTN]; + stageys[2] <= ysprop[`MAXOUTN]; + stagers[2] <= mrs[`MAXOUTN]; + stageis[2] <= mis[`MAXOUTN]; + stageb[2] <= mb[`MAXOUTN]; + stageci[2] <= curiter[`MAXOUTN]; + end + + if (state[2]) begin // PnR2 in, PnR1 out + stagex[1] <= xprop[`MAXOUTN]; + stagey[1] <= yprop[`MAXOUTN]; + stager[1] <= mr[`MAXOUTN]; + stagei[1] <= mi[`MAXOUTN]; + stagexs[1] <= xsprop[`MAXOUTN]; + stageys[1] <= ysprop[`MAXOUTN]; + stagers[1] <= mrs[`MAXOUTN]; + stageis[1] <= mis[`MAXOUTN]; + stageb[1] <= mb[`MAXOUTN]; + stageci[1] <= curiter[`MAXOUTN]; + end end MandelUnit mu0( @@ -312,9 +367,6 @@ module Mandelbrot( MandelUnit mub(mclk, xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10], xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]); - MandelUnit muc(mclk, - xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11], - xprop[12], yprop[12], xsprop[12], ysprop[12], mr[12], mi[12], mrs[12], mis[12], mb[12], curiter[12]); endmodule @@ -344,10 +396,26 @@ module MandelTop( input left, right, up, down, rst, cycle, logooff, input [2:0] scale); + + wire pixclk, mclk, gclk2, clk; + wire dcm1ok, dcm2ok; + assign dcmok = dcm1ok && dcm2ok; + + IBUFG typeA(.O(clk), .I(gclk)); + + pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz + .CLKIN_IN(clk), + .CLKFX_OUT(pixclk), + .LOCKED_OUT(dcm1ok) + ); + + mandelDCM dcm2( + .CLKIN_IN(clk), + .CLKFX_OUT(mclk), + .LOCKED_OUT(dcm2ok) + ); + wire border; - wire pixclk; - wire [7:0] zero = 8'b0; - wire clk; wire [11:0] x, y; reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2; reg [5:0] slowctr = 0; @@ -358,15 +426,8 @@ module MandelTop( wire [2:0] mandelr, mandelg, logor, logog; wire [1:0] mandelb, logob; - pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz - .CLKIN_IN(gclk), - .CLKFX_OUT(pixclk), - .CLKIN_IBUFG_OUT(clk), - .LOCKED_OUT(dcmok) - ); - SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border); - Mandelbrot mandel(clk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb); + Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb); Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob); assign {red,green,blue} =