X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/772b24130eddc406758d19b13ef30686a82030cc..ae4b5d43c85753328c337c98de6406df5e263d7d:/Main.v?ds=sidebyside

diff --git a/Main.v b/Main.v
index 165a095..aa3d861 100644
--- a/Main.v
+++ b/Main.v
@@ -10,7 +10,9 @@
 
 `define XRES 640
 `define YRES 480
-`define WHIRRRRR 27
+`define WHIRRRRR 47
+
+`define TOPBIT 13
 
 module SyncGen(
 	input pixclk,
@@ -62,28 +64,31 @@ endmodule
 
 module NaiveMultiplier(
 	input clk,
-	input [12:0] x, y,
+	input [`TOPBIT:0] x, y,
 	input xsign, ysign,
-	output reg [12:0] out,
+	output reg [`TOPBIT:0] out,
 	output reg sign,
 	output reg ovf);
 
 	always @(posedge clk)
 	begin
 		{ovf,out} <=
-			(((y[12] ? (x       ) : 0)   +
-			  (y[11] ? (x[12:1]) : 0)   +
-			  (y[10] ? (x[12:2]) : 0))  +
-			(((y[9]  ? (x[12:3]) : 0)   +
-			  (y[8]  ? (x[12:4]) : 0))  +
-			 ((y[7]  ? (x[12:5]) : 0)   +
-			  (y[6]  ? (x[12:6]) : 0))))+
-			(((y[5]  ? (x[12:7]) : 0)   +
-			  (y[4]  ? (x[12:8]) : 0)   +
-			  (y[3]  ? (x[12:9]) : 0))  +
-			 ((y[2]  ? (x[12:10]): 0)   +
-			  (y[1]  ? (x[12:11]): 0)   +
-			  (y[0]  ? (x[12]): 0)));
+		       ((((0)                            + // 15
+			  (0))                           + // 14
+			 ((y[13] ? (x           ) : 0)   +
+			  (y[12] ? (x[`TOPBIT:1]) : 0))) +
+			(((y[11] ? (x[`TOPBIT:2]) : 0)   +
+			  (y[10] ? (x[`TOPBIT:3]) : 0))  +
+			 ((y[9]  ? (x[`TOPBIT:4]) : 0)   +
+			  (y[8]  ? (x[`TOPBIT:5]) : 0))))+
+		       ((((y[7]  ? (x[`TOPBIT:6]) : 0)   +
+			  (y[6]  ? (x[`TOPBIT:7]) : 0))  +
+			 ((y[5]  ? (x[`TOPBIT:8]) : 0)   +
+			  (y[4]  ? (x[`TOPBIT:9]) : 0))) +
+			(((y[3]  ? (x[`TOPBIT:10]): 0)   +
+			  (y[2]  ? (x[`TOPBIT:11]): 0))  +
+			 ((y[1]  ? (x[`TOPBIT:12]): 0)   +
+			  (y[0]  ? (x[`TOPBIT])   : 0))));
 		sign <= xsign ^ ysign;
 	end
 
@@ -91,9 +96,9 @@ endmodule
 
 module Multiplier(
 	input clk,
-	input [12:0] x, y,
+	input [`TOPBIT:0] x, y,
 	input xsign, ysign,
-	output wire [12:0] out,
+	output wire [`TOPBIT:0] out,
 	output wire sign,
 	output wire overflow);
 
@@ -104,44 +109,44 @@ endmodule
 // Yuq.
 module MandelUnit(
 	input clk,
-	input [12:0] x, y,
+	input [`TOPBIT:0] x, y,
 	input xsign, ysign,
-	input [14:0] r, i,
+	input [`TOPBIT+2:0] r, i,
 	input rsign, isign,
 	input [7:0] ibail, icuriter,
-	output reg [12:0] xout, yout,
+	output reg [`TOPBIT:0] xout, yout,
 	output reg xsout, ysout,
-	output reg [14:0] rout, iout,
+	output reg [`TOPBIT+2:0] rout, iout,
 	output reg rsout, isout,
 	output reg [7:0] obail, ocuriter);
 
-	wire [13:0] r2, i2;
-	wire [14:0] ri, diff;
-	wire [15:0] twocdiff;
+	wire [`TOPBIT+1:0] r2, i2;
+	wire [`TOPBIT+2:0] ri, diff;
+	wire [`TOPBIT+3:0] twocdiff;
 	wire r2sign, i2sign, risign, dsign;
-	wire [14:0] bigsum;
+	wire [`TOPBIT+2:0] bigsum;
 	wire bigsum_ovf;
 
-	reg [12:0] xd, yd;
+	reg [`TOPBIT:0] xd, yd;
 	reg ineedbaild;
 	reg xsd, ysd;
 	reg [7:0] ibaild, curiterd;
 
 	assign ri[0] = 0;
 
-	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
-	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
-	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
+	Multiplier r2m(clk, r[`TOPBIT:0], r[`TOPBIT:0], rsign, rsign, r2[`TOPBIT:0], r2sign, r2[`TOPBIT+1]);
+	Multiplier i2m(clk, i[`TOPBIT:0], i[`TOPBIT:0], isign, isign, i2[`TOPBIT:0], i2sign, i2[`TOPBIT+1]);
+	Multiplier rim(clk, r[`TOPBIT:0], i[`TOPBIT:0], rsign, isign, ri[`TOPBIT+1:1], risign, ri[`TOPBIT+2]);
 
-	assign bigsum = r2[13:0] + i2[13:0];
-	assign bigsum_ovf = bigsum[14];
+	assign bigsum = r2[`TOPBIT+1:0] + i2[`TOPBIT+1:0];
+	assign bigsum_ovf = bigsum[`TOPBIT+2];
 	
 	assign twocdiff = r2 - i2;
-	assign diff = twocdiff[15] ? -twocdiff : twocdiff;
-	assign dsign = twocdiff[15];
+	assign diff = twocdiff[`TOPBIT+3] ? -twocdiff : twocdiff;
+	assign dsign = twocdiff[`TOPBIT+3];
 	
-	wire [15:0] twocrout = xd - diff;
-	wire [15:0] twociout = yd - ri;
+	wire [`TOPBIT+3:0] twocrout = xd - diff;
+	wire [`TOPBIT+3:0] twociout = yd - ri;
 
 	always @ (posedge clk)
 	begin
@@ -155,11 +160,11 @@ module MandelUnit(
 		ysout <= ysd;
 		ibaild <= ibail;
 		curiterd <= icuriter;
-		ineedbaild <= r[13] | r[14] | i[13] | i[14];
+		ineedbaild <= r[`TOPBIT+1] | r[`TOPBIT+2] | i[`TOPBIT+1] | i[`TOPBIT+2];
 
 		// r^2 - i^2 + x
 		if (xsd ^ dsign) begin
-			if (twocrout[15]) begin	// diff > xd
+			if (twocrout[`TOPBIT+3]) begin	// diff > xd
 				rout <= -twocrout;
 				rsout <= dsign;
 			end else begin
@@ -173,7 +178,7 @@ module MandelUnit(
 		
 		// 2 * r * i + y
 		if (ysd ^ risign) begin
-			if (twociout[15]) begin	// ri > yd
+			if (twociout[`TOPBIT+3]) begin	// ri > yd
 				iout <= -twociout;
 				isout <= risign;
 			end else begin
@@ -200,39 +205,39 @@ module Mandelbrot(
 	input mclk,
 	input pixclk,
 	input [11:0] x, y,
-	input [13:0] xofs, yofs,
+	input [`TOPBIT+1:0] xofs, yofs,
 	input [7:0] colorofs,
 	input [2:0] scale,
 	output reg [2:0] red, green, output reg [1:0] blue);
 
-`define MAXOUTN 11
+`define MAXOUTN 21
 	
-	wire [12:0] rx, ry;
-	wire [13:0] nx, ny;
+	wire [`TOPBIT:0] rx, ry;
+	wire [`TOPBIT+1:0] nx, ny;
 	wire rxsign, rysign;
 	
 	assign nx = {2'b0,x} + {2'b0,xofs};
 	assign ny = {2'b0,y} + {2'b0,yofs};
-	assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
-	assign rxsign = nx[13];
-	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
-	assign rysign = ny[13];
+	assign rx = (nx[`TOPBIT+1] ? -nx[`TOPBIT:0] : nx[`TOPBIT:0]) << scale;
+	assign rxsign = nx[`TOPBIT+1];
+	assign ry = (ny[`TOPBIT+1] ? -ny[`TOPBIT:0] : ny[`TOPBIT:0]) << scale;
+	assign rysign = ny[`TOPBIT+1];
 
-	wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
+	wire [`TOPBIT+2:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
 	wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
 	wire [7:0] mb[`MAXOUTN:0];
-	wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
+	wire [`TOPBIT:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
 	wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
 	wire [7:0] curiter[`MAXOUTN:0];
 	
-	reg [12:0] initx, inity;
-	reg [14:0] initr, initi;
+	reg [`TOPBIT:0] initx, inity;
+	reg [`TOPBIT+2:0] initr, initi;
 	reg [7:0] initci, initb;
 	reg initxs, initys, initrs, initis;
 	
 	// Values after the number of iterations denoted by the subscript.
-	reg [12:0] stagex [2:1], stagey [2:1];
-	reg [14:0] stager [2:1], stagei [2:1];
+	reg [`TOPBIT:0] stagex [2:1], stagey [2:1];
+	reg [`TOPBIT+2:0] stager [2:1], stagei [2:1];
 	reg [7:0] stageci [2:1], stageb [2:1];
 	reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
 	
@@ -292,7 +297,9 @@ module Mandelbrot(
 			3'b001: state <= 3'b010;
 			3'b010: state <= 3'b100;
 			3'b100: state <= 3'b001;
+		`ifdef isim
 			default: begin $display("invalid state"); $finish; end
+		`endif
 			endcase
 	
 		// Data output handling
@@ -355,6 +362,16 @@ module Mandelbrot(
 	`MAKE_UNIT(mu9, 8);
 	`MAKE_UNIT(mua, 9);
 	`MAKE_UNIT(mub, 10);
+	`MAKE_UNIT(muc, 11);
+	`MAKE_UNIT(mud, 12);
+	`MAKE_UNIT(mue, 13);
+	`MAKE_UNIT(muf, 14);
+	`MAKE_UNIT(mug, 15);
+	`MAKE_UNIT(muh, 16);
+	`MAKE_UNIT(mui, 17);
+	`MAKE_UNIT(muj, 18);
+	`MAKE_UNIT(muk, 19);
+	`MAKE_UNIT(mul, 20);
 endmodule
 
 module Logo(
@@ -410,7 +427,7 @@ module MandelTop(
 
 	wire border;
 	wire [11:0] x, y;
-	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
+	reg [`TOPBIT+1:0] xofs = -`XRES/2, yofs = -`YRES/2;
 	reg [5:0] slowctr = 0;
 	reg [7:0] colorcycle = 0;
 	wire [11:0] realx, realy;