X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/534b3903d1e1d0a58b620c01e947a1c81c47f124..265061f2b080c0ea2b18d0a1f7b92de658a5ad92:/Main.v?ds=sidebyside

diff --git a/Main.v b/Main.v
index 61cb8f1..ad8e90c 100644
--- a/Main.v
+++ b/Main.v
@@ -230,11 +230,6 @@ module Mandelbrot(
 	
 	reg [2:0] state = 3'b001;	// One-hot encoded state.
 	
-	// On pixclk = 1,
-	//    A new value to be loaded comes in, and a value in need of loopback comes out.
-	// On pixclk = 0,
-	//    A new value in need of loopback comes in, and a completed value comes out.
-	
 	assign initx = state[0] ? rx :
 	               state[1] ? stagex[1] :
 	               stagex[2];
@@ -263,22 +258,20 @@ module Mandelbrot(
 	               state[1] ? stageb[1] :
 	               stageb[2];
 	assign initci = state[0] ? 8'b00000000 :
-	                state[1] ? stageb[1] : 
-	                stageb[2];
+	                state[1] ? stageci[1] : 
+	                stageci[2];
 	
 	reg [7:0] out;
 	reg typethea = 0;	// Whether we have typed the A.
 	reg statekick = 0;	// State needs to be kicked back to 3'b010 on the next mclk.
 
 	// This is guaranteed to converge after two pixclks.
-	//always @(negedge mclk)
-	//	if (pixclk && !typethea) begin
-	//		typethea <= 1;
-	//		statekick <= 1;
-	//	end else if (typethea) begin // This is the edge of the falling anus.
-	//		typethea <= 0;
-	//		statekick <= 0;
-	//	end
+	always @(negedge mclk)
+		if (pixclk && !statekick) begin
+			statekick <= 1;
+		end else if (statekick) begin // This is the edge of the falling anus.
+			statekick <= 0;
+		end
 	
 	always @(posedge mclk)
 	begin
@@ -286,11 +279,11 @@ module Mandelbrot(
 		if (state[0]) begin
 			{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
 		end
-		if (state[2]) begin
+		if (state[1]) begin
 			out <= ~mb[`MAXOUTN] + colorofs;
 		end
 		
-		if (state[1]) begin		// PnR0 in, PnR2 out
+		if (state[0]) begin		// PnR0 in, PnR2 out
 			stagex[2] <= xprop[`MAXOUTN];
 			stagey[2] <= yprop[`MAXOUTN];
 			stager[2] <= mr[`MAXOUTN];
@@ -303,7 +296,7 @@ module Mandelbrot(
 			stageci[2] <= curiter[`MAXOUTN];
 		end
 		
-		if (state[0]) begin	// PnR2 in, PnR1 out
+		if (state[2]) begin	// PnR2 in, PnR1 out
 			stagex[1] <= xprop[`MAXOUTN];
 			stagey[1] <= yprop[`MAXOUTN];
 			stager[1] <= mr[`MAXOUTN];
@@ -396,21 +389,28 @@ module MandelTop(
 
 	wire pixclk, mclk, gclk2, clk;
 	wire dcm1ok, dcm2ok;
-	assign dcmok = dcm1ok && dcm2ok;
+	//assign dcmok = dcm1ok && dcm2ok;
+	
+	//IBUFG typeA(.O(clk), .I(gclk));
 	
-	IBUFG typeA(.O(clk), .I(gclk));
+	//pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
+	//	.CLKIN_IN(clk), 
+	//	.CLKFX_OUT(pixclk),
+	//	.LOCKED_OUT(dcm1ok)
+	//	);
 	
-	pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
-		.CLKIN_IN(clk), 
-		.CLKFX_OUT(pixclk),
-		.LOCKED_OUT(dcm1ok)
-		);
+	//mandelDCM dcm2(
+	//	.CLKIN_IN(clk),
+	//	.CLKFX_OUT(mclk),
+	//	.LOCKED_OUT(dcm2ok)
+	//	);
 	
-	mandelDCM dcm2(
-		.CLKIN_IN(clk),
-		.CLKFX_OUT(mclk),
-		.LOCKED_OUT(dcm2ok)
-		);
+	mainDCM dcm (
+    .U1_CLKIN_IN(gclk), 
+    .U1_CLKDV_OUT(pixclk), 
+    .U2_CLKFX_OUT(mclk), 
+    .U2_LOCKED_OUT(dcmok)
+    );
 	
 	wire border;
 	wire [11:0] x, y;