X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/3068fa611c7bfac974131f874165b002b5f20607..fb8d158b6c717854cc1697eea6f9013fb401c805:/Main.v

diff --git a/Main.v b/Main.v
index 11d7833..b034663 100644
--- a/Main.v
+++ b/Main.v
@@ -64,22 +64,23 @@ module NaiveMultiplier(
 	input xsign, ysign,
 	output reg [12:0] out,
 	output reg sign,
-	output reg [1:0] ovf);
+	output reg ovf);
 
 	always @(posedge clk)
 	begin
 		{ovf,out} <=
 			(((y[12] ? (x     ) : 0)  +
 			  (y[11] ? (x >> 1) : 0)  +
-			  (y[10] ? (x >> 2) : 0)  +
-			  (y[9]  ? (x >> 3) : 0)) +
-			 ((y[8]  ? (x >> 4) : 0)  +
-			  (y[7]  ? (x >> 5) : 0)  +
-			  (y[6]  ? (x >> 6) : 0)))+
+			  (y[10] ? (x >> 2) : 0)) +
+			(((y[9]  ? (x >> 3) : 0)  +
+			  (y[8]  ? (x >> 4) : 0))+
+		    ((y[7]  ? (x >> 5) : 0)  +
+			  (y[6]  ? (x >> 6) : 0))))+
+			  
 			(((y[5]  ? (x >> 7) : 0)  +
-			  (y[4]  ? (x >> 8) : 0)  +
+			  (y[4]  ? (x >> 8) : 0)+
 			  (y[3]  ? (x >> 9) : 0)) +
-			 ((y[2]  ? (x >> 10): 0)  +
+			 ((y[2]  ? (x >> 10): 0) +
 			  (y[1]  ? (x >> 11): 0)  +
 			  (y[0]  ? (x >> 12): 0)));
 		sign <= xsign ^ ysign;
@@ -93,12 +94,13 @@ module Multiplier(
 	input xsign, ysign,
 	output wire [12:0] out,
 	output wire sign,
-	output wire [1:0] overflow);
+	output wire overflow);
 
 	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
 
 endmodule
 
+// Yuq.
 module MandelUnit(
 	input clk,
 	input [12:0] x, y,
@@ -262,21 +264,21 @@ module Mandelbrot(
 	                stageci[2];
 	
 	reg [7:0] out;
-	reg typethea = 0;	// Whether we have typed the A.
-	reg statekick = 0;	// State needs to be kicked back to 3'b010 on the next mclk.
-
-	// This is guaranteed to converge after two pixclks.
-	//always @(negedge mclk)
-	//	if (pixclk && !typethea) begin
-	//		typethea <= 1;
-	//		statekick <= 1;
-	//	end else if (typethea) begin // This is the edge of the falling anus.
-	//		typethea <= 0;
-	//		statekick <= 0;
-	//	end
+	
+	// We detect when the state should be poked by a high negedge followed
+	// by a high posedge -- if that happens, then we're guaranteed that the
+	// state following the current state will be 3'b100.
+	reg lastneg;
+	always @(negedge mclk)
+		lastneg <= pixclk;
 	
 	always @(posedge mclk)
 	begin
+		if (lastneg && pixclk)	// If a pixclk has happened, the state should be reset.
+			state <= 3'b100;
+		else						// Otherwise, just poke it forward.
+			state <= {state[1], state[0], state[2]};
+	
 		// Data output handling
 		if (state[0]) begin
 			{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
@@ -310,11 +312,6 @@ module Mandelbrot(
 			stageb[1] <= mb[`MAXOUTN];
 			stageci[1] <= curiter[`MAXOUTN];
 		end
-		
-		if (statekick)		// If a pixclk has happened, the state should be reset.
-			state <= 3'b010;
-		else						// Otherwise, just poke it forward.
-			state <= {state[1], state[0], state[2]};
 	end
 
 	MandelUnit mu0(