X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/3068fa611c7bfac974131f874165b002b5f20607..265061f2b080c0ea2b18d0a1f7b92de658a5ad92:/Main.v

diff --git a/Main.v b/Main.v
index 11d7833..ad8e90c 100644
--- a/Main.v
+++ b/Main.v
@@ -266,14 +266,12 @@ module Mandelbrot(
 	reg statekick = 0;	// State needs to be kicked back to 3'b010 on the next mclk.
 
 	// This is guaranteed to converge after two pixclks.
-	//always @(negedge mclk)
-	//	if (pixclk && !typethea) begin
-	//		typethea <= 1;
-	//		statekick <= 1;
-	//	end else if (typethea) begin // This is the edge of the falling anus.
-	//		typethea <= 0;
-	//		statekick <= 0;
-	//	end
+	always @(negedge mclk)
+		if (pixclk && !statekick) begin
+			statekick <= 1;
+		end else if (statekick) begin // This is the edge of the falling anus.
+			statekick <= 0;
+		end
 	
 	always @(posedge mclk)
 	begin
@@ -391,21 +389,28 @@ module MandelTop(
 
 	wire pixclk, mclk, gclk2, clk;
 	wire dcm1ok, dcm2ok;
-	assign dcmok = dcm1ok && dcm2ok;
+	//assign dcmok = dcm1ok && dcm2ok;
+	
+	//IBUFG typeA(.O(clk), .I(gclk));
 	
-	IBUFG typeA(.O(clk), .I(gclk));
+	//pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
+	//	.CLKIN_IN(clk), 
+	//	.CLKFX_OUT(pixclk),
+	//	.LOCKED_OUT(dcm1ok)
+	//	);
 	
-	pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
-		.CLKIN_IN(clk), 
-		.CLKFX_OUT(pixclk),
-		.LOCKED_OUT(dcm1ok)
-		);
+	//mandelDCM dcm2(
+	//	.CLKIN_IN(clk),
+	//	.CLKFX_OUT(mclk),
+	//	.LOCKED_OUT(dcm2ok)
+	//	);
 	
-	mandelDCM dcm2(
-		.CLKIN_IN(clk),
-		.CLKFX_OUT(mclk),
-		.LOCKED_OUT(dcm2ok)
-		);
+	mainDCM dcm (
+    .U1_CLKIN_IN(gclk), 
+    .U1_CLKDV_OUT(pixclk), 
+    .U2_CLKFX_OUT(mclk), 
+    .U2_LOCKED_OUT(dcmok)
+    );
 	
 	wire border;
 	wire [11:0] x, y;