X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/265061f2b080c0ea2b18d0a1f7b92de658a5ad92..a3a4354bafd8467e9b79c037314da6644f41b470:/Main.v diff --git a/Main.v b/Main.v index ad8e90c..aacfdab 100644 --- a/Main.v +++ b/Main.v @@ -64,22 +64,23 @@ module NaiveMultiplier( input xsign, ysign, output reg [12:0] out, output reg sign, - output reg [1:0] ovf); + output reg ovf); always @(posedge clk) begin {ovf,out} <= (((y[12] ? (x ) : 0) + (y[11] ? (x >> 1) : 0) + - (y[10] ? (x >> 2) : 0) + - (y[9] ? (x >> 3) : 0)) + - ((y[8] ? (x >> 4) : 0) + - (y[7] ? (x >> 5) : 0) + - (y[6] ? (x >> 6) : 0)))+ + (y[10] ? (x >> 2) : 0)) + + (((y[9] ? (x >> 3) : 0) + + (y[8] ? (x >> 4) : 0))+ + ((y[7] ? (x >> 5) : 0) + + (y[6] ? (x >> 6) : 0))))+ + (((y[5] ? (x >> 7) : 0) + - (y[4] ? (x >> 8) : 0) + + (y[4] ? (x >> 8) : 0)+ (y[3] ? (x >> 9) : 0)) + - ((y[2] ? (x >> 10): 0) + + ((y[2] ? (x >> 10): 0) + (y[1] ? (x >> 11): 0) + (y[0] ? (x >> 12): 0))); sign <= xsign ^ ysign; @@ -93,12 +94,13 @@ module Multiplier( input xsign, ysign, output wire [12:0] out, output wire sign, - output wire [1:0] overflow); + output wire overflow); NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow); endmodule +// Yuq. module MandelUnit( input clk, input [12:0] x, y, @@ -115,7 +117,7 @@ module MandelUnit( wire [14:0] r2, i2, ri, diff; wire [15:0] twocdiff; wire r2sign, i2sign, risign, dsign; - wire [16:0] bigsum; + wire [15:0] bigsum; wire bigsum_ovf, rin_ovf, iin_ovf, throwaway; reg [12:0] xd, yd; @@ -125,12 +127,12 @@ module MandelUnit( assign ri[0] = 0; - Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]); - Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]); - Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]}); + Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]); + Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]); + Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]); assign bigsum = r2 + i2; - assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14]; + assign bigsum_ovf = bigsum[15] | bigsum[14]; assign rin_ovf = rd; assign iin_ovf = id; assign twocdiff = r2 - i2; @@ -210,7 +212,6 @@ module Mandelbrot( assign rxsign = nx[13]; assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale; assign rysign = ny[13]; - wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0]; wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0]; @@ -230,51 +231,57 @@ module Mandelbrot( reg [2:0] state = 3'b001; // One-hot encoded state. - assign initx = state[0] ? rx : - state[1] ? stagex[1] : - stagex[2]; - assign inity = state[0] ? ry : - state[1] ? stagey[1] : - stagey[2]; - assign initr = state[0] ? rx : - state[1] ? stager[1] : - stager[2]; - assign initi = state[0] ? ry : - state[1] ? stagei[1] : - stagei[2]; - assign initxs = state[0] ? rxsign : - state[1] ? stagexs[1] : - stagexs[2]; - assign initys = state[0] ? rysign : - state[1] ? stageys[1] : - stageys[2]; - assign initrs = state[0] ? rxsign : - state[1] ? stagers[1] : - stagers[2]; - assign initis = state[0] ? rysign : - state[1] ? stageis[1] : - stageis[2]; - assign initb = state[0] ? 8'b11111111 : - state[1] ? stageb[1] : - stageb[2]; - assign initci = state[0] ? 8'b00000000 : - state[1] ? stageci[1] : - stageci[2]; + assign initx = (state[0]) ? rx : + (state[1]) ? stagex[1] : + (state[2]) ? stagex[2] : 0; + assign inity = (state[0]) ? ry : + (state[1]) ? stagey[1] : + (state[2]) ? stagey[2] : 0; + assign initr = (state[0]) ? rx : + (state[1]) ? stager[1] : + (state[2]) ? stager[2] : 0; + assign initi = (state[0]) ? ry : + (state[1]) ? stagei[1] : + (state[2]) ? stagei[2] : 0; + assign initxs = (state[0]) ? rxsign : + (state[1]) ? stagexs[1] : + (state[2]) ? stagexs[2] : 0; + assign initys = (state[0]) ? rysign : + (state[1]) ? stageys[1] : + (state[2]) ? stageys[2] : 0; + assign initrs = (state[0]) ? rxsign : + (state[1]) ? stagers[1] : + (state[2]) ? stagers[2] : 0; + assign initis = (state[0]) ? rysign : + (state[1]) ? stageis[1] : + (state[2]) ? stageis[2] : 0; + assign initb = (state[0]) ? 8'b11111111 : + (state[1]) ? stageb[1] : + (state[2]) ? stageb[2] : 0; + assign initci = (state[0]) ? 8'b00000000 : + (state[1]) ? stageci[1] : + (state[2]) ? stageci[2] : 0; reg [7:0] out; - reg typethea = 0; // Whether we have typed the A. - reg statekick = 0; // State needs to be kicked back to 3'b010 on the next mclk. - - // This is guaranteed to converge after two pixclks. + + // We detect when the state should be poked by a high negedge followed + // by a high posedge -- if that happens, then we're guaranteed that the + // state following the current state will be 3'b100. + reg lastneg; always @(negedge mclk) - if (pixclk && !statekick) begin - statekick <= 1; - end else if (statekick) begin // This is the edge of the falling anus. - statekick <= 0; - end + lastneg <= pixclk; always @(posedge mclk) begin + if (lastneg && pixclk) // If a pixclk has happened, the state should be reset. + state <= 3'b100; + else // Otherwise, just poke it forward. + case(state) + 3'b001: state <= 3'b010; + 3'b010: state <= 3'b100; + 3'b100: state <= 3'b001; + endcase + // Data output handling if (state[0]) begin {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]}; @@ -308,11 +315,6 @@ module Mandelbrot( stageb[1] <= mb[`MAXOUTN]; stageci[1] <= curiter[`MAXOUTN]; end - - if (statekick) // If a pixclk has happened, the state should be reset. - state <= 3'b010; - else // Otherwise, just poke it forward. - state <= {state[1], state[0], state[2]}; end MandelUnit mu0( @@ -389,28 +391,21 @@ module MandelTop( wire pixclk, mclk, gclk2, clk; wire dcm1ok, dcm2ok; - //assign dcmok = dcm1ok && dcm2ok; - - //IBUFG typeA(.O(clk), .I(gclk)); + assign dcmok = dcm1ok && dcm2ok; - //pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz - // .CLKIN_IN(clk), - // .CLKFX_OUT(pixclk), - // .LOCKED_OUT(dcm1ok) - // ); + IBUFG typeA(.O(clk), .I(gclk)); - //mandelDCM dcm2( - // .CLKIN_IN(clk), - // .CLKFX_OUT(mclk), - // .LOCKED_OUT(dcm2ok) - // ); + pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz + .CLKIN_IN(clk), + .CLKFX_OUT(pixclk), + .LOCKED_OUT(dcm1ok) + ); - mainDCM dcm ( - .U1_CLKIN_IN(gclk), - .U1_CLKDV_OUT(pixclk), - .U2_CLKFX_OUT(mclk), - .U2_LOCKED_OUT(dcmok) - ); + mandelDCM dcm2( + .CLKIN_IN(clk), + .CLKFX_OUT(mclk), + .LOCKED_OUT(dcm2ok) + ); wire border; wire [11:0] x, y;