X-Git-Url: http://git.joshuawise.com/mandelfpga.git/blobdiff_plain/251788d85bd34ae72b677875e924d56768b409f7..fb8d158b6c717854cc1697eea6f9013fb401c805:/Main.v

diff --git a/Main.v b/Main.v
index 3dc546b..b034663 100644
--- a/Main.v
+++ b/Main.v
@@ -64,22 +64,23 @@ module NaiveMultiplier(
 	input xsign, ysign,
 	output reg [12:0] out,
 	output reg sign,
-	output reg [1:0] ovf);
+	output reg ovf);
 
 	always @(posedge clk)
 	begin
 		{ovf,out} <=
 			(((y[12] ? (x     ) : 0)  +
 			  (y[11] ? (x >> 1) : 0)  +
-			  (y[10] ? (x >> 2) : 0)  +
-			  (y[9]  ? (x >> 3) : 0)) +
-			 ((y[8]  ? (x >> 4) : 0)  +
-			  (y[7]  ? (x >> 5) : 0)  +
-			  (y[6]  ? (x >> 6) : 0)))+
+			  (y[10] ? (x >> 2) : 0)) +
+			(((y[9]  ? (x >> 3) : 0)  +
+			  (y[8]  ? (x >> 4) : 0))+
+		    ((y[7]  ? (x >> 5) : 0)  +
+			  (y[6]  ? (x >> 6) : 0))))+
+			  
 			(((y[5]  ? (x >> 7) : 0)  +
-			  (y[4]  ? (x >> 8) : 0)  +
+			  (y[4]  ? (x >> 8) : 0)+
 			  (y[3]  ? (x >> 9) : 0)) +
-			 ((y[2]  ? (x >> 10): 0)  +
+			 ((y[2]  ? (x >> 10): 0) +
 			  (y[1]  ? (x >> 11): 0)  +
 			  (y[0]  ? (x >> 12): 0)));
 		sign <= xsign ^ ysign;
@@ -93,12 +94,13 @@ module Multiplier(
 	input xsign, ysign,
 	output wire [12:0] out,
 	output wire sign,
-	output wire [1:0] overflow);
+	output wire overflow);
 
 	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
 
 endmodule
 
+// Yuq.
 module MandelUnit(
 	input clk,
 	input [12:0] x, y,
@@ -264,8 +266,8 @@ module Mandelbrot(
 	reg [7:0] out;
 	
 	// We detect when the state should be poked by a high negedge followed
-	// by a high posedge -- if tha thappens, then we're guaranteed that the
-	// state following the current state will be 100.
+	// by a high posedge -- if that happens, then we're guaranteed that the
+	// state following the current state will be 3'b100.
 	reg lastneg;
 	always @(negedge mclk)
 		lastneg <= pixclk;
@@ -386,28 +388,21 @@ module MandelTop(
 
 	wire pixclk, mclk, gclk2, clk;
 	wire dcm1ok, dcm2ok;
-	//assign dcmok = dcm1ok && dcm2ok;
+	assign dcmok = dcm1ok && dcm2ok;
 	
-	//IBUFG typeA(.O(clk), .I(gclk));
+	IBUFG typeA(.O(clk), .I(gclk));
 	
-	//pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
-	//	.CLKIN_IN(clk), 
-	//	.CLKFX_OUT(pixclk),
-	//	.LOCKED_OUT(dcm1ok)
-	//	);
+	pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
+		.CLKIN_IN(clk), 
+		.CLKFX_OUT(pixclk),
+		.LOCKED_OUT(dcm1ok)
+		);
 	
-	//mandelDCM dcm2(
-	//	.CLKIN_IN(clk),
-	//	.CLKFX_OUT(mclk),
-	//	.LOCKED_OUT(dcm2ok)
-	//	);
-	
-	mainDCM dcm (
-    .U1_CLKIN_IN(gclk), 
-    .U1_CLKDV_OUT(pixclk), 
-    .U2_CLKFX_OUT(mclk), 
-    .U2_LOCKED_OUT(dcmok)
-    );
+	mandelDCM dcm2(
+		.CLKIN_IN(clk),
+		.CLKFX_OUT(mclk),
+		.LOCKED_OUT(dcm2ok)
+		);
 	
 	wire border;
 	wire [11:0] x, y;