descriptionPipelined realtime renderer of the Mandelbrot set on a Xilinx FPGA
ownerJoshua Wise
last changeWed, 9 Jul 2008 17:49:05 +0000 (13:49 -0400)
MandelFPGA is a real-time pipelined Mandelbrot set renderer running on Digilent Nexys2 boards. This project was a collaboration between myself and Christopher Lu -- for more information on the inner workings on it, please refer to his excellent writeup on it.



Questions? Comments? Problems? Joshua Wise <joshua at joshuawise dot com> or Chris Lu <chris at lulabs dot net>
2008-07-09 Joshua WiseAdd the UCF. master
2008-07-09 Joshua WiseAdded logo.readmemb
2008-07-09 Joshua WiseOne more fixup
2008-07-09 Joshua WiseAdd needed files for build; I r retard.
2008-07-09 Christopher Luadded mandelsim.c
2008-07-09 Joshua WiseAdd another bit.
2008-07-09 Joshua WiseConvert to xc3s1200e, add more units, prepare to add...
2008-07-08 Joshua Wisebring in the make buildsystem for MandelFPGA
2008-07-08 Joshua Wisebring in the make buildsystem for MandelFPGA
2008-06-19 Joshua WiseAdd support for Verilator
2008-03-28 Joshua WiseHoly crap, dropped lut count to 7640, and slice count...
2008-03-28 Joshua WiseProd/cons-ify readout so it can do realtime
2008-03-28 Joshua WiseAdd readout
2008-03-28 Joshua WiseSomething that works
2008-03-28 Joshua Wisenew ctoreadmemb
2008-03-28 Joshua Wisepoke the clock with a stick
10 years ago PRE_ROLLBACK
10 years ago master
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