From f8db64484a25b6970acb75b35188efd7089e572a Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sat, 5 Apr 2008 00:34:42 -0400 Subject: [PATCH] Cut 1 at interrupt support for CPU --- FPGABoy.ise | Bin 240410 -> 240439 bytes GBZ80Core.v | 60 +++++++++++++++++++++++++++++++++++++++++++++++++--- System.v | 18 ++++++++++------ 3 files changed, 69 insertions(+), 9 deletions(-) diff --git a/FPGABoy.ise b/FPGABoy.ise index 227845500b0c7f94cfbe06aa62cec21e47c4f84e..3562e2939347135378f2138caa6b9fb7e0726134 100644 GIT binary patch delta 12997 zcma)Cdt6ji*PgwBnKO(B#Y^L$pfI4wZ5Wj6h>8d!0wN+RDk3P}5E11f3SKiSue>W< znp#<}rIi(0jihK=<`wVP%v)wFa z_46K<^B$l0d$}%aYHACCUdzS1!bOciA^ju41onAp$uPL&^*Wv11Q9NU94)SCeCJYpRewsG1=OaBf-0Km`5L?I<5(` znWlGzoX!SasLDi9C(wD)eE?QCt4P6Z6B;4*|2>3%OYQn7yiVKT{NSdwg5~%IEnEVDEe9dGKOyH4XHg1>N|dxcDdQ-0cj zm+6n17+X9;n}t9=mieCWA3Jg!h|}FD2;vrR`^Skvf2MVagh+KiMP$bz&4N*U?zKEQ-GF~Lqk9oSp#A> zldc;*!Us#gFMP<;i~Jb!yP1uCu4YZ7E$G#4H3AQ`YL}`P4{Pits*QYN`mNEp+sCp%WA`wc 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z+4l3-bcMTQvCaLSnyGtqbVM|MafrTQA0-~9wf51a!*s4R3dh_dvMsy|K088-nJqj9 zCmyBi?4!oV=!eoM9KSe5OWdQQ;^HviIQ^I1cJ??uXdk_Qg4Wna(I@Fb`{=8acII## zeu{3j+dNOxH`Eee71kf3k$Cbn^|sGEI8D>+WyfIeGc1;*3GO_@a+gQF&eDpe(kLdX zO4U21f3KXhq~6&6G*j&6S(?vXnS{-8%sD!N8&001@8i`UsDLxh(?UDfo%3|OWD_y# z0554{Xl2SJZxOv}%kWP4WY7SlrG{)yDT{|BAbpe6tS diff --git a/GBZ80Core.v b/GBZ80Core.v index 095d9e8..57c22d2 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -46,6 +46,9 @@ `define INSN_JR_imm 8'b00011000 `define INSN_JRCC_imm 8'b001xx000 `define INSN_INCDEC16 8'b00xxx011 +`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending. +`define INSN_DI 8'b11110011 +`define INSN_EI 8'b11111011 `define INSN_cc_NZ 2'b00 `define INSN_cc_Z 2'b01 @@ -89,7 +92,8 @@ module GBZ80Core( input clk, output reg [15:0] busaddress = 0, /* BUS_* is latched on STATE_FETCH. */ inout [7:0] busdata, - output reg buswr = 0, output reg busrd = 0); + output reg buswr = 0, output reg busrd = 0, + input irq, input [7:0] jaddr); reg [1:0] state = 0; /* State within this bus cycle (see STATE_*). */ reg [2:0] cycle = 0; /* Cycle for instructions. */ @@ -108,7 +112,7 @@ module GBZ80Core( reg [7:0] buswdata; assign busdata = buswr ? buswdata : 8'bzzzzzzzz; - reg ie = 0; + reg ie = 0, iedelay = 0; initial begin registers[ 0] <= 0; @@ -129,6 +133,10 @@ module GBZ80Core( newcycle <= 1; state <= 0; cycle <= 0; + busrd <= 0; + buswr <= 0; + busaddress <= 0; + iedelay <= 0; end always @(posedge clk) @@ -149,7 +157,10 @@ module GBZ80Core( end `STATE_DECODE: begin if (newcycle) begin - opcode <= busdata; + if (ie && irq) + opcode <= `INSN_VOP_INTR; + else + opcode <= busdata; rdata <= busdata; newcycle <= 0; cycle <= 0; @@ -157,6 +168,10 @@ module GBZ80Core( if (rd) rdata <= busdata; cycle <= cycle + 1; end + if (iedelay) begin + ie <= 1; + iedelay <= 0; + end buswr <= 0; busrd <= 0; wr <= 0; @@ -552,6 +567,31 @@ module GBZ80Core( end endcase end + `INSN_VOP_INTR: begin + case (cycle) + 0: begin + address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; + wdata <= registers[`REG_PCH]; + wr <= 1; + end + 1: begin + address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; + wdata <= registers[`REG_PCL]; + wr <= 1; + end + 2: begin + `EXEC_NEWCYCLE; + end + endcase + end + `INSN_DI: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end + `INSN_EI: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end default: $stop; endcase @@ -896,6 +936,20 @@ module GBZ80Core( end endcase end + `INSN_VOP_INTR: begin + case (cycle) + 0: begin end + 1: {registers[`REG_SPH],registers[`REG_SPL]} + <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; + 2: begin + ie <= 0; + {registers[`REG_PCH],registers[`REG_PCL]} <= + {8'b0,jaddr}; + end + endcase + end + `INSN_DI: ie <= 0; + `INSN_EI: iedelay <= 1; default: $stop; endcase diff --git a/System.v b/System.v index 8b8d613..7319ebf 100644 --- a/System.v +++ b/System.v @@ -76,13 +76,18 @@ module CoreTop( wire [15:0] addr; wire [7:0] data; wire wr, rd; + + wire irq, tmrirq; + wire [7:0] jaddr; GBZ80Core core( .clk(clk), .busaddress(addr), .busdata(data), .buswr(wr), - .busrd(rd)); + .busrd(rd), + .irq(irq), + .jaddr(jaddr)); ROM rom( .address(addr), @@ -125,8 +130,6 @@ module CoreTop( .wr(wr), .rd(rd)); - wire irq, tmrirq; - wire [7:0] jaddr; Timer tmr( .clk(clk), .wr(wr), @@ -156,6 +159,9 @@ module TestBench(); wire [7:0] data; wire wr, rd; + wire irq, tmrirq; + wire [7:0] jaddr; + // wire [7:0] leds; // wire [7:0] switches; @@ -165,7 +171,9 @@ module TestBench(); .busaddress(addr), .busdata(data), .buswr(wr), - .busrd(rd)); + .busrd(rd), + .irq(irq), + .jaddr(jaddr)); ROM rom( .clk(clk), @@ -190,8 +198,6 @@ module TestBench(); .rd(rd), .serial(serio)); - wire irq, tmrirq; - wire [7:0] jaddr; Timer tmr( .clk(clk), .wr(wr), -- 2.43.0