From df770340caf8ecd26a55179484edb507082bd5c6 Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sun, 6 Apr 2008 03:34:31 -0400 Subject: [PATCH] Finish splitting out functions. --- GBZ80Core.v | 384 ++++++--------------------------------------- allinsns.v | 9 ++ insn_call-callcc.v | 57 +++++++ insn_di-ei.v | 11 ++ insn_incdec16.v | 59 +++++++ insn_jp-jpcc.v | 43 +++++ insn_jp_hl.v | 12 ++ insn_jr-jrcc.v | 38 +++++ insn_ret-retcc.v | 48 ++++++ insn_rst.v | 36 +++++ insn_vop_intr.v | 35 +++++ 11 files changed, 395 insertions(+), 337 deletions(-) create mode 100644 insn_call-callcc.v create mode 100644 insn_di-ei.v create mode 100644 insn_incdec16.v create mode 100644 insn_jp-jpcc.v create mode 100644 insn_jp_hl.v create mode 100644 insn_jr-jrcc.v create mode 100644 insn_ret-retcc.v create mode 100644 insn_rst.v create mode 100644 insn_vop_intr.v diff --git a/GBZ80Core.v b/GBZ80Core.v index f41805a..e085739 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -1,59 +1,59 @@ -`define REG_A 0 -`define REG_B 1 -`define REG_C 2 -`define REG_D 3 -`define REG_E 4 -`define REG_F 5 -`define REG_H 6 -`define REG_L 7 -`define REG_SPH 8 -`define REG_SPL 9 -`define REG_PCH 10 -`define REG_PCL 11 +`define REG_A 0 +`define REG_B 1 +`define REG_C 2 +`define REG_D 3 +`define REG_E 4 +`define REG_F 5 +`define REG_H 6 +`define REG_L 7 +`define REG_SPH 8 +`define REG_SPL 9 +`define REG_PCH 10 +`define REG_PCL 11 -`define FLAG_Z 8'b10000000 -`define FLAG_N 8'b01000000 -`define FLAG_H 8'b00100000 -`define FLAG_C 8'b00010000 +`define FLAG_Z 8'b10000000 +`define FLAG_N 8'b01000000 +`define FLAG_H 8'b00100000 +`define FLAG_C 8'b00010000 -`define STATE_FETCH 2'h0 -`define STATE_DECODE 2'h1 +`define STATE_FETCH 2'h0 +`define STATE_DECODE 2'h1 `define STATE_EXECUTE 2'h2 `define STATE_WRITEBACK 2'h3 `define INSN_LD_reg_imm8 8'b00xxx110 -`define INSN_HALT 8'b01110110 +`define INSN_HALT 8'b01110110 `define INSN_LD_HL_reg 8'b01110xxx `define INSN_LD_reg_HL 8'b01xxx110 `define INSN_LD_reg_reg 8'b01xxxxxx `define INSN_LD_reg_imm16 8'b00xx0001 `define INSN_LD_SP_HL 8'b11111001 `define INSN_PUSH_reg 8'b11xx0101 -`define INSN_POP_reg 8'b11xx0001 -`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A -`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A -`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy -`define INSN_NOP 8'b00000000 -`define INSN_RST 8'b11xxx111 -`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET -`define INSN_RETCC 8'b110xx000 -`define INSN_CALL 8'b11001101 -`define INSN_CALLCC 8'b110xx100 // Not that call/cc. -`define INSN_JP_imm 8'b11000011 +`define INSN_POP_reg 8'b11xx0001 +`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A +`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A +`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy +`define INSN_NOP 8'b00000000 +`define INSN_RST 8'b11xxx111 +`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET +`define INSN_RETCC 8'b110xx000 +`define INSN_CALL 8'b11001101 +`define INSN_CALLCC 8'b110xx100 // Not that call/cc. +`define INSN_JP_imm 8'b11000011 `define INSN_JPCC_imm 8'b110xx010 `define INSN_ALU_A 8'b00xxx111 -`define INSN_JP_HL 8'b11101001 -`define INSN_JR_imm 8'b00011000 +`define INSN_JP_HL 8'b11101001 +`define INSN_JR_imm 8'b00011000 `define INSN_JRCC_imm 8'b001xx000 `define INSN_INCDEC16 8'b00xxx011 `define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending. -`define INSN_DI 8'b11110011 -`define INSN_EI 8'b11111011 +`define INSN_DI 8'b11110011 +`define INSN_EI 8'b11111011 -`define INSN_cc_NZ 2'b00 -`define INSN_cc_Z 2'b01 -`define INSN_cc_NC 2'b10 -`define INSN_cc_C 2'b11 +`define INSN_cc_NZ 2'b00 +`define INSN_cc_Z 2'b01 +`define INSN_cc_NC 2'b10 +`define INSN_cc_C 2'b11 `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 @@ -62,15 +62,15 @@ `define INSN_reg_E 3'b011 `define INSN_reg_H 3'b100 `define INSN_reg_L 3'b101 -`define INSN_reg_dHL 3'b110 -`define INSN_reg16_BC 2'b00 -`define INSN_reg16_DE 2'b01 -`define INSN_reg16_HL 2'b10 -`define INSN_reg16_SP 2'b11 -`define INSN_stack_AF 2'b11 -`define INSN_stack_BC 2'b00 -`define INSN_stack_DE 2'b01 -`define INSN_stack_HL 2'b10 +`define INSN_reg_dHL 3'b110 +`define INSN_reg16_BC 2'b00 +`define INSN_reg16_DE 2'b01 +`define INSN_reg16_HL 2'b10 +`define INSN_reg16_SP 2'b11 +`define INSN_stack_AF 2'b11 +`define INSN_stack_BC 2'b00 +`define INSN_stack_DE 2'b01 +`define INSN_stack_HL 2'b10 `define INSN_alu_ADD 3'b000 `define INSN_alu_ADC 3'b001 `define INSN_alu_SUB 3'b010 @@ -194,195 +194,6 @@ module GBZ80Core( `define EXECUTE `include "allinsns.v" `undef EXECUTE - `INSN_RST: begin - case (cycle) - 0: begin - `EXEC_INC_PC; // This goes FIRST in RST - end - 1: begin - wr <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; - wdata <= registers[`REG_PCH]; - end - 2: begin - wr <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}-2; - wdata <= registers[`REG_PCL]; - end - 3: begin - `EXEC_NEWCYCLE; - {registers[`REG_PCH],registers[`REG_PCL]} <= - {10'b0,opcode[5:3],3'b0}; - end - endcase - end - `INSN_RET,`INSN_RETCC: begin - case (cycle) - 0: begin - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}; - end - 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret! - `EXEC_INC_PC; // cycle 1 is skipped if we are not retcc - case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - endcase - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}; - end - 2: begin - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1; - end - 3: begin /* twiddle thumbs */ end - 4: begin - `EXEC_NEWCYCLE; - // do NOT increment PC! - end - endcase - end - `INSN_CALL,`INSN_CALLCC: begin - case (cycle) - 0: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; - end - 1: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; - end - 2: begin - `EXEC_INC_PC; - if (!opcode[0]) // i.e., is callcc - /* We need to check the condition code to bail out. */ - case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - endcase - end - 3: begin - address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; - wdata <= registers[`REG_PCH]; - wr <= 1; - end - 4: begin - address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; - wdata <= registers[`REG_PCL]; - wr <= 1; - end - 5: begin - `EXEC_NEWCYCLE; /* do NOT increment the PC */ - end - endcase - end - `INSN_JP_imm,`INSN_JPCC_imm: begin - case (cycle) - 0: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; - end - 1: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; - end - 2: begin - `EXEC_INC_PC; - if (!opcode[0]) begin // i.e., JP cc,nn - /* We need to check the condition code to bail out. */ - case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - endcase - end - end - 3: begin - `EXEC_NEWCYCLE; - end - endcase - end - `INSN_JP_HL: begin - `EXEC_NEWCYCLE; - end - `INSN_JR_imm,`INSN_JRCC_imm: begin - case (cycle) - 0: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; - end - 1: begin - `EXEC_INC_PC; - if (opcode[5]) begin // i.e., JP cc,nn - /* We need to check the condition code to bail out. */ - case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - endcase - end - end - 2: begin - `EXEC_NEWCYCLE; - end - endcase - end - `INSN_INCDEC16: begin - case (cycle) - 0: begin - case (opcode[5:4]) - `INSN_reg16_BC: begin - tmp <= registers[`REG_B]; - tmp2 <= registers[`REG_C]; - end - `INSN_reg16_DE: begin - tmp <= registers[`REG_D]; - tmp2 <= registers[`REG_E]; - end - `INSN_reg16_HL: begin - tmp <= registers[`REG_H]; - tmp2 <= registers[`REG_L]; - end - `INSN_reg16_SP: begin - tmp <= registers[`REG_SPH]; - tmp2 <= registers[`REG_SPL]; - end - endcase - end - 1: begin - `EXEC_INC_PC; - `EXEC_NEWCYCLE; - end - endcase - end - `INSN_VOP_INTR: begin - case (cycle) - 0: begin - address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; - wdata <= registers[`REG_PCH]; - wr <= 1; - end - 1: begin - address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; - wdata <= registers[`REG_PCL]; - wr <= 1; - end - 2: begin - `EXEC_NEWCYCLE; - end - endcase - end `INSN_DI: begin `EXEC_NEWCYCLE; `EXEC_INC_PC; @@ -401,107 +212,6 @@ module GBZ80Core( `define WRITEBACK `include "allinsns.v" `undef WRITEBACK - `INSN_RST: begin - case (cycle) - 0: begin /* type F */ end - 1: begin /* type F */ end - 2: begin /* type F */ end - 3: {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]}-2; - endcase - end - `INSN_RET,`INSN_RETCC: begin - case (cycle) - 0: if (opcode[0]) // i.e., not RETCC - cycle <= 1; // Skip cycle 1; it gets incremented on the next round. - 1: begin /* Nothing need happen here. */ end - 2: registers[`REG_PCL] <= rdata; - 3: registers[`REG_PCH] <= rdata; - 4: begin - {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]} + 2; - if (opcode[4] && opcode[0]) /* RETI */ - ie <= 1; - end - endcase - end - `INSN_CALL,`INSN_CALLCC: begin - case (cycle) - 0: begin /* type F */ end - 1: tmp <= rdata; // tmp contains newpcl - 2: tmp2 <= rdata; // tmp2 contains newpch - 3: begin /* type F */ end - 4: registers[`REG_PCH] <= tmp2; - 5: begin - {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]} - 2; - registers[`REG_PCL] <= tmp; - end - endcase - end - `INSN_JP_imm,`INSN_JPCC_imm: begin - case (cycle) - 0: begin /* type F */ end - 1: tmp <= rdata; // tmp contains newpcl - 2: tmp2 <= rdata; // tmp2 contains newpch - 3: {registers[`REG_PCH],registers[`REG_PCL]} <= - {tmp2,tmp}; - endcase - end - `INSN_JP_HL: begin - {registers[`REG_PCH],registers[`REG_PCL]} <= - {registers[`REG_H],registers[`REG_L]}; - end - `INSN_JR_imm,`INSN_JRCC_imm: begin - case (cycle) - 0: begin /* type F */ end - 1: tmp <= rdata; - 2: {registers[`REG_PCH],registers[`REG_PCL]} <= - {registers[`REG_PCH],registers[`REG_PCL]} + - {tmp[7]?8'hFF:8'h00,tmp}; - endcase - end - `INSN_INCDEC16: begin - case (cycle) - 0: {tmp,tmp2} <= {tmp,tmp2} + - (opcode[3] ? 16'hFFFF : 16'h0001); - 1: begin - case (opcode[5:4]) - `INSN_reg16_BC: begin - registers[`REG_B] <= tmp; - registers[`REG_C] <= tmp2; - end - `INSN_reg16_DE: begin - registers[`REG_D] <= tmp; - registers[`REG_E] <= tmp2; - end - `INSN_reg16_HL: begin - registers[`REG_H] <= tmp; - registers[`REG_L] <= tmp2; - end - `INSN_reg16_SP: begin - registers[`REG_SPH] <= tmp; - registers[`REG_SPL] <= tmp2; - end - endcase - end - endcase - end - `INSN_VOP_INTR: begin - case (cycle) - 0: begin end - 1: begin end - 2: begin - ie <= 0; - {registers[`REG_PCH],registers[`REG_PCL]} <= - {8'b0,jaddr}; - {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]} - 2; - end - endcase - end - `INSN_DI: ie <= 0; - `INSN_EI: iedelay <= 1; default: $stop; endcase diff --git a/allinsns.v b/allinsns.v index 79d88aa..fbcca50 100644 --- a/allinsns.v +++ b/allinsns.v @@ -12,3 +12,12 @@ `include "insn_alu8.v" `include "insn_alu_a.v" `include "insn_nop.v" +`include "insn_rst.v" +`include "insn_ret-retcc.v" +`include "insn_call-callcc.v" +`include "insn_jp-jpcc.v" +`include "insn_jp_hl.v" +`include "insn_jr-jrcc.v" +`include "insn_incdec16.v" +`include "insn_vop_intr.v" +`include "insn_di-ei.v" diff --git a/insn_call-callcc.v b/insn_call-callcc.v new file mode 100644 index 0000000..bb7c14a --- /dev/null +++ b/insn_call-callcc.v @@ -0,0 +1,57 @@ +`ifdef EXECUTE + `INSN_CALL,`INSN_CALLCC: begin + case (cycle) + 0: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 1: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 2: begin + `EXEC_INC_PC; + if (!opcode[0]) // i.e., is callcc + /* We need to check the condition code to bail out. */ + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + end + 3: begin + address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; + wdata <= registers[`REG_PCH]; + wr <= 1; + end + 4: begin + address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; + wdata <= registers[`REG_PCL]; + wr <= 1; + end + 5: begin + `EXEC_NEWCYCLE; /* do NOT increment the PC */ + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_CALL,`INSN_CALLCC: begin + case (cycle) + 0: begin /* type F */ end + 1: tmp <= rdata; // tmp contains newpcl + 2: tmp2 <= rdata; // tmp2 contains newpch + 3: begin /* type F */ end + 4: registers[`REG_PCH] <= tmp2; + 5: begin + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} - 2; + registers[`REG_PCL] <= tmp; + end + endcase + end +`endif diff --git a/insn_di-ei.v b/insn_di-ei.v new file mode 100644 index 0000000..3b06578 --- /dev/null +++ b/insn_di-ei.v @@ -0,0 +1,11 @@ +`ifdef EXECUTE + `INSN_DI,`INSN_EI: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end +`endif + +`ifdef WRITEBACK + `INSN_DI: ie <= 0; + `INSN_EI: iedelay <= 1; +`endif diff --git a/insn_incdec16.v b/insn_incdec16.v new file mode 100644 index 0000000..01f919c --- /dev/null +++ b/insn_incdec16.v @@ -0,0 +1,59 @@ +`ifdef EXECUTE + `INSN_INCDEC16: begin + case (cycle) + 0: begin + case (opcode[5:4]) + `INSN_reg16_BC: begin + tmp <= registers[`REG_B]; + tmp2 <= registers[`REG_C]; + end + `INSN_reg16_DE: begin + tmp <= registers[`REG_D]; + tmp2 <= registers[`REG_E]; + end + `INSN_reg16_HL: begin + tmp <= registers[`REG_H]; + tmp2 <= registers[`REG_L]; + end + `INSN_reg16_SP: begin + tmp <= registers[`REG_SPH]; + tmp2 <= registers[`REG_SPL]; + end + endcase + end + 1: begin + `EXEC_INC_PC; + `EXEC_NEWCYCLE; + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_INCDEC16: begin + case (cycle) + 0: {tmp,tmp2} <= {tmp,tmp2} + + (opcode[3] ? 16'hFFFF : 16'h0001); + 1: begin + case (opcode[5:4]) + `INSN_reg16_BC: begin + registers[`REG_B] <= tmp; + registers[`REG_C] <= tmp2; + end + `INSN_reg16_DE: begin + registers[`REG_D] <= tmp; + registers[`REG_E] <= tmp2; + end + `INSN_reg16_HL: begin + registers[`REG_H] <= tmp; + registers[`REG_L] <= tmp2; + end + `INSN_reg16_SP: begin + registers[`REG_SPH] <= tmp; + registers[`REG_SPL] <= tmp2; + end + endcase + end + endcase + end +`endif diff --git a/insn_jp-jpcc.v b/insn_jp-jpcc.v new file mode 100644 index 0000000..2b2e52b --- /dev/null +++ b/insn_jp-jpcc.v @@ -0,0 +1,43 @@ +`ifdef EXECUTE + `INSN_JP_imm,`INSN_JPCC_imm: begin + case (cycle) + 0: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 1: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 2: begin + `EXEC_INC_PC; + if (!opcode[0]) begin // i.e., JP cc,nn + /* We need to check the condition code to bail out. */ + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + end + end + 3: begin + `EXEC_NEWCYCLE; + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_JP_imm,`INSN_JPCC_imm: begin + case (cycle) + 0: begin /* type F */ end + 1: tmp <= rdata; // tmp contains newpcl + 2: tmp2 <= rdata; // tmp2 contains newpch + 3: {registers[`REG_PCH],registers[`REG_PCL]} <= + {tmp2,tmp}; + endcase + end +`endif diff --git a/insn_jp_hl.v b/insn_jp_hl.v new file mode 100644 index 0000000..4ee380a --- /dev/null +++ b/insn_jp_hl.v @@ -0,0 +1,12 @@ +`ifdef EXECUTE + `INSN_JP_HL: begin + `EXEC_NEWCYCLE; + end +`endif + +`ifdef WRITEBACK + `INSN_JP_HL: begin + {registers[`REG_PCH],registers[`REG_PCL]} <= + {registers[`REG_H],registers[`REG_L]}; + end +`endif diff --git a/insn_jr-jrcc.v b/insn_jr-jrcc.v new file mode 100644 index 0000000..7a869b3 --- /dev/null +++ b/insn_jr-jrcc.v @@ -0,0 +1,38 @@ +`ifdef EXECUTE + `INSN_JR_imm,`INSN_JRCC_imm: begin + case (cycle) + 0: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 1: begin + `EXEC_INC_PC; + if (opcode[5]) begin // i.e., JP cc,nn + /* We need to check the condition code to bail out. */ + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + end + end + 2: begin + `EXEC_NEWCYCLE; + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_JR_imm,`INSN_JRCC_imm: begin + case (cycle) + 0: begin /* type F */ end + 1: tmp <= rdata; + 2: {registers[`REG_PCH],registers[`REG_PCL]} <= + {registers[`REG_PCH],registers[`REG_PCL]} + + {tmp[7]?8'hFF:8'h00,tmp}; + endcase + end +`endif diff --git a/insn_ret-retcc.v b/insn_ret-retcc.v new file mode 100644 index 0000000..ef89003 --- /dev/null +++ b/insn_ret-retcc.v @@ -0,0 +1,48 @@ +`ifdef EXECUTE + `INSN_RET,`INSN_RETCC: begin + case (cycle) + 0: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}; + end + 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret! + `EXEC_INC_PC; // cycle 1 is skipped if we are not retcc + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}; + end + 2: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1; + end + 3: begin /* twiddle thumbs */ end + 4: begin + `EXEC_NEWCYCLE; + // do NOT increment PC! + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_RET,`INSN_RETCC: begin + case (cycle) + 0: if (opcode[0]) // i.e., not RETCC + cycle <= 1; // Skip cycle 1; it gets incremented on the next round. + 1: begin /* Nothing need happen here. */ end + 2: registers[`REG_PCL] <= rdata; + 3: registers[`REG_PCH] <= rdata; + 4: begin + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} + 2; + if (opcode[4] && opcode[0]) /* RETI */ + ie <= 1; + end + endcase + end +`endif diff --git a/insn_rst.v b/insn_rst.v new file mode 100644 index 0000000..8752034 --- /dev/null +++ b/insn_rst.v @@ -0,0 +1,36 @@ +`ifdef EXECUTE + `INSN_RST: begin + case (cycle) + 0: begin + `EXEC_INC_PC; // This goes FIRST in RST + end + 1: begin + wr <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; + wdata <= registers[`REG_PCH]; + end + 2: begin + wr <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}-2; + wdata <= registers[`REG_PCL]; + end + 3: begin + `EXEC_NEWCYCLE; + {registers[`REG_PCH],registers[`REG_PCL]} <= + {10'b0,opcode[5:3],3'b0}; + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_RST: begin + case (cycle) + 0: begin /* type F */ end + 1: begin /* type F */ end + 2: begin /* type F */ end + 3: {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]}-2; + endcase + end +`endif diff --git a/insn_vop_intr.v b/insn_vop_intr.v new file mode 100644 index 0000000..134d462 --- /dev/null +++ b/insn_vop_intr.v @@ -0,0 +1,35 @@ +`ifdef EXECUTE + `INSN_VOP_INTR: begin + case (cycle) + 0: begin + address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; + wdata <= registers[`REG_PCH]; + wr <= 1; + end + 1: begin + address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; + wdata <= registers[`REG_PCL]; + wr <= 1; + end + 2: begin + `EXEC_NEWCYCLE; + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_VOP_INTR: begin + case (cycle) + 0: begin end + 1: begin end + 2: begin + ie <= 0; + {registers[`REG_PCH],registers[`REG_PCL]} <= + {8'b0,jaddr}; + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} - 2; + end + endcase + end +`endif -- 2.39.2