From 94522011a1aecc56d0718817bd4ffeb6b650b308 Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sun, 30 Mar 2008 05:42:47 -0400 Subject: [PATCH 1/1] Our first ALU operation -- ADD --- FPGABoy.ise | Bin 209616 -> 209616 bytes GBZ80Core.v | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ rom.hex | 8 +++++--- 3 files changed, 57 insertions(+), 3 deletions(-) diff --git a/FPGABoy.ise b/FPGABoy.ise index c05d0ea731329d33db5981eda7f126771ba33eac..d4eace857545ebea2b19984911444d7dda45ad2b 100644 GIT binary patch delta 1858 zcma)6e{54#6n^KvuJ)I%MZm-?Ze|)2RNT7KRwEm8GPRbi`_ZmgjLitNb+C;#8;CR8 zfQW394M%d6RghvB>te!0c$$Dtl0{w6At6epi9fo=s}AMUN@%PKMUzkKQM#uxu8!Ks6o$@ z&}ZR{{xgEGMi3vu4_t5;THH_}rh+$NgBuPRQ$c+ujW3Mz?zBn{c&C`kg+*0Vb#5Ir zDr9dSuBd`$64c|NDi}1#nn%XbQ4KFEI3GWw*eu_dhgnWPuCAsz`#n%ef;#-t1A{U} z+x<18gwawGV-n1TI2u$6uGjt(XjfIbRmGUgbhT2n!)56G{i+ucbJ& z8CtnR>*I|09dk%!Ih2Q>{=XesPH|zD!!IFd=MF7eM*NmJ{FdeLS{VF`91L;~%^oa> zz*1mUOHV`qfZxU5mFk}bpGFCsmfmRwCuL};5&bR?NY`7SJ%X#V)lVh%0xi1sf!?2j)#&Ffoj}18RX!GQ9$QM6sxm5(mL!R03~H z^GD#kQuTBbetZ<}=Y(iA9(@a(nA-$8EK5MHAxOtbKZ4iMpMbmb>S!n0lMqp`?_a+`7;hO>{{~y7u2J~hto+fAW8f@o;CS*3eyGM%SEPH+ z!L?PKaJe7z=ioMurz5y#4xF0vrssyFjyX8HOzX5;9VJCrswasYM^TZr1ZVW*C3ake zQ3Kh*jy6mgNK7V&jbw|)>aaeDSB&HsBUrJ^M0ztv$$T@}OVVeDb8kGCNby|JR`?Ix C54H*b delta 1862 zcma)6ZETZO6n@WrSL_#S3)}c3+sqV|sj#l=HY;qkXjv&;-AC72aB%|b6aih<8AD_s z0i|;~H*;i6n1u-2{DJY~4GCxzNt6IVeyGuy=ww?Y+DT@_;l{kZrT2E$AHKitIrn+a z^PF?@o{OXUi=+DEQ{x#U?T_E}{>-?kNsg&MM3W2N(#5(1QvB1dS%@cG&?yqGo#Vr7#PGzmuGnNaNdnoJFT4)krXDcrC zz!qZLfPEh5(b_gJFSlG6!P07YMZ_MwKx1R_{`?VE(~m2vY0X!?@G!A8;Wu9BNkZhv zM+_1|Qw@b2d<33IR+IO=fVvt{O@7(IpqmoVb2ah4=y(>?LYJ^=cj9nuYG0K$#tP$m zwNzkp9W;qaRrImDw#1!W538uZo+4EaHr7Lgdvvrg*lz6h(Gt176ps&9V8oZ=(M|_L zXTK`}bvML2Zp7XOc$2r4pNm$%7@C}W4bRhlCDYe z6?*;wO=}?=r#6C%z!+Z5frU8K492`9Q98kik`$7f8BMbEz~5PTU=wUhDyU~W8Sp2j zFp;KUZ-%=6R8ZfT;>0wC-xbVIgQwdIm?1pJQCoK6K)!nItRf_&~=p-CK>`Js3ygHHSRi+QYXTo*)Rs7;@ zxL0Gh&~ed462b1XkcGx5+<}ItK#dhqFlcR!>{fGS7X9?*R@-_O8!`jZ$MKVMBAJ!XnWKXku;2MR=; zb*MfHPm40`xZ^0ecO=bb2IRq;_7l5{{ut8uoQzEWUAj40iwTUpctCEQo1r@>Z47b; z!|?qZ-zw6Ac?EDug|1_;N0@vJzdHuc2$K(C{U8+EIkRd^_RX#3Y?Usv%tXpgP4kUk z4$@zq&)kmIA!reC&cEK^Zp<7`eS;R$ zSl+hiwok&z?0KbS=AzZRgu+PT8^U{@{-EB+-kAl zvs&^TJDPDqOInlQkdAE5pa3&|t0RZwfZ}rO(342ws2Jyyy+ma-TP-Df`wc|tH^`QP Fe*odAuj>E+ diff --git a/GBZ80Core.v b/GBZ80Core.v index b7994ae..0cdefa5 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -32,6 +32,7 @@ `define INSN_POP_reg 8'b11xx0001 `define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A `define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A +`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 @@ -49,6 +50,15 @@ `define INSN_stack_BC 2'b00 `define INSN_stack_DE 2'b01 `define INSN_stack_HL 2'b10 +`define INSN_alu_ADD 3'b000 +`define INSN_alu_ADC 3'b001 +`define INSN_alu_SUB 3'b010 +`define INSN_alu_SBC 3'b011 +`define INSN_alu_AND 3'b100 +`define INSN_alu_XOR 3'b101 +`define INSN_alu_OR 3'b110 +`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP? + module GBZ80Core( input clk, output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */ @@ -303,6 +313,26 @@ module GBZ80Core( end endcase end + `INSN_ALU8: begin + if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin + // fffffffff fuck your shit, read from (HL) :( + rd <= 1; + address <= {registers[`REG_H], registers[`REG_L]}; + end else begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + case (opcode[2:0]) + `INSN_reg_A: begin tmp <= registers[`REG_A]; end + `INSN_reg_B: begin tmp <= registers[`REG_B]; end + `INSN_reg_C: begin tmp <= registers[`REG_C]; end + `INSN_reg_D: begin tmp <= registers[`REG_D]; end + `INSN_reg_E: begin tmp <= registers[`REG_E]; end + `INSN_reg_H: begin tmp <= registers[`REG_H]; end + `INSN_reg_L: begin tmp <= registers[`REG_L]; end + `INSN_reg_dHL: begin tmp <= rdata; end + endcase + end + end default: $stop; endcase @@ -467,6 +497,28 @@ module GBZ80Core( end endcase end + `INSN_ALU8: begin + if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin + /* Sit on our asses. */ + cycle <= 1; + end else begin /* Actually do the computation! */ + case (opcode[5:3]) + `INSN_alu_ADD: begin + registers[`REG_A] <= + registers[`REG_A] + tmp; + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0, + /* N */ 0, + /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0, + /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0, + registers[`REG_F][3:0] + }; + end + default: + $stop; + endcase + end + end endcase state <= `STATE_FETCH; end diff --git a/rom.hex b/rom.hex index c86844c..6142c98 100644 --- a/rom.hex +++ b/rom.hex @@ -6,9 +6,11 @@ F9 // POP BC C1 -// LD A, 12h +// LD A, 10h 3E -12 +10 +// ADD C +81 // LD H, A 67 // LD L, 34h @@ -20,5 +22,5 @@ C1 76 @100 -50 +02 56 -- 2.43.0