From 75be7c71a363261fa7ba96ee2a667ec753e478bb Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sat, 19 Apr 2008 00:08:57 -0400 Subject: [PATCH 1/1] Fix tileaddr bug. Make bus interface more explicit. --- LCDC.v | 32 ++++++++++++++++---------------- diag.asm | 10 ++++++---- 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/LCDC.v b/LCDC.v index a8bec01..9a111f7 100644 --- a/LCDC.v +++ b/LCDC.v @@ -137,7 +137,7 @@ module LCDC( // The new tile data is latched and ready when vxpos[2:0] is 3'b000! wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]}; reg [7:0] tileno; - wire [10:0] tileaddr = {tileno, vypos[2:1]}; + wire [10:0] tileaddr = {tileno, vypos[2:0]}; reg [7:0] tilehigh, tilelow; assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]}; @@ -166,21 +166,21 @@ module LCDC( /***** Bus interface *****/ assign data = rd ? - (addr == `ADDR_LCDC) ? rLCDC : - (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} : - (addr == `ADDR_SCY) ? rSCY : - (addr == `ADDR_SCX) ? rSCX : - (addr == `ADDR_LY) ? posy : - (addr == `ADDR_LYC) ? rLYC : - (addr == `ADDR_BGP) ? rBGP : - (addr == `ADDR_OBP0) ? rOBP0 : - (addr == `ADDR_OBP1) ? rOBP1 : - (addr == `ADDR_WY) ? rWY : - (addr == `ADDR_WX) ? rWX : - (decode_tiledata && addr[0]) ? tilehigh : - (decode_tiledata && ~addr[0]) ? tilelow : - (decode_bgmap1) ? tileno : - 8'bzzzzzzzz : + ((addr == `ADDR_LCDC) ? rLCDC : + (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} : + (addr == `ADDR_SCY) ? rSCY : + (addr == `ADDR_SCX) ? rSCX : + (addr == `ADDR_LY) ? posy : + (addr == `ADDR_LYC) ? rLYC : + (addr == `ADDR_BGP) ? rBGP : + (addr == `ADDR_OBP0) ? rOBP0 : + (addr == `ADDR_OBP1) ? rOBP1 : + (addr == `ADDR_WY) ? rWY : + (addr == `ADDR_WX) ? rWX : + (decode_tiledata && addr[0]) ? tilehigh : + (decode_tiledata && ~addr[0]) ? tilelow : + (decode_bgmap1) ? tileno : + 8'bzzzzzzzz) : 8'bzzzzzzzz; always @(negedge clk) diff --git a/diag.asm b/diag.asm index bc164a0..5d44cef 100644 --- a/diag.asm +++ b/diag.asm @@ -52,10 +52,12 @@ signon: putscreen: ; Wait for vblank -;.stat: ld a, [$FF41] ; STAT -; and $03 ; mode -; cp $01 ; VBLANK -;' jp nz, .stat + ld c, $41 +.stat: ld a, [c] + ld [$FF51], a + and $03 ; mode + cp $01 ; VBLANK + jr nz, .stat ld hl, $8000 ; Copy two tiles. ld a, $AA -- 2.43.0